Senior SOC Design Engineer - Networking Group

NVIDIA Gruppe; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Benefits offered by this job

Competitive salary

Comprehensive benefits package

Job summary

NVIDIA Gruppe in Bengaluru, India is seeking an expert SOC Design and Integration Engineer to join the Networking chip design group. You’ll impact developing high-speed communication devices, aiming for efficiency and low latency. Engage with a team crafting the next generation DPU and Switch Silicon chips.

This role entails defining project milestones, working with SOC Assembly teams, and integrating project elements. Looking for individuals with a BS/MS and 3+ years in semiconductor design.

Qualifications

• 3+ years of practical semiconductor design and architecture experience.
• Solid understanding of all phases of SOC development.
• Experience with design and verification tools.
• Hands-on experience in successful tape outs of SoCs.

Responsibilities

• Define project milestones and track them through an agile framework.
• Work with SOC Assembly team to drive milestone execution.
• Integrate all pieces for project milestones and deliver the model.
• Develop methodologies and tools for efficient subsystem building.

Skills

SOC Development

Verilog/SV

C/C++ programming

Python scripting

Communication

Education

BS/MS in semiconductor design

Tools

Cadence

GDB

Job description

We are currently seeking an expert SOC Design and Integration Engineer with strong design fundamentals to work in the Networking chip design group. You’ll join a group of hardworking engineers to craft and implement the next generation innovative DPUs and Switch Silicon chips. In this position, you’ll make a real impact in a dynamic, technology‑focused company while developing best high‑speed communication devices, delivering the highest efficiency and lowest latency. The Networking Chip Design team in India is a new team which is growing at a fast pace.

What you’ll be doing:

• You are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through an agile framework.
• Define and develop system‑level methodologies, tools, and IPs to build subsystems in an efficient and scalable manner.
• Work with SOC Assembly team and drive cross‑functional teams towards SOC milestone execution.
• Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub‑system/SOC/emulation levels.

What we need to see:

• BS (or equivalent experience) / MS with 3+ years of practical semiconductor design and architecture experience building complex SoC’s.
• Must have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, micro‑architecture, RTL design, verification, timing closure & physical design.
• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).
• C/C++ programming or python or any other industry‑standard scripting language experience desirable.
• Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.
• Hands on experience in successful tape outs of multiple sophisticated, high‑volume SoCs in advanced process nodes.
• Exposure to various Chip Design Functions to be able to collaborate and tackle sophisticated cross functional problems.
• Excellent verbal and written communication skills to interact with cross functional teams to build consensus.
• Experience in synthesis, physical design and DFT is a plus.
• Experience in RTL Build and Design Automation is a plus.

Ways to Stand out from the crowd:

• Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.
• Experience in RTL coding and debug, as well as performance/power/area analysis and trade‑offs.
• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.
• Prior experience of smartNIC and/or high‑speed interconnects.
• Strong coding skills in Perl, Python, or other industry‑standard scripting languages.

Known throughout the technology industry as a top employer, NVIDIA delivers highly competitive salaries and a thorough benefits package. As you plan your future, see what we can offer to you and your family https://www.nvidiabenefits.com/

NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.