Senior Analog Circuit Design Engineer

Univision Technology Solutions Pvt Ltd (UTS) ); Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Equity options

Competitive compensation

Collaborative environment

Job summary

Univision Technology Solutions Pvt Ltd (UTS) is seeking a Senior Analog Circuit Design Engineer in Bengaluru. You will lead architecture, design, and silicon validation of high-performance analog/mixed-signal blocks for readout circuits used in sensor platforms.

The role emphasizes low-noise signal conditioning, high-density data conversion, and ultra-low-power operation with end-to-end ownership from specification to tape-out.

Qualifications

• Bachelor’s/Master’s/Ph.D. in Electrical Engineering or related field.
• 12–15 years of hands-on analog IC design experience.
• Expertise in low-noise analog design and data converters.

Responsibilities

• Own end-to-end design lifecycle for ultra-low-power analog IC blocks.
• Design LNAs, PGAs, and bandgap references for sensor readouts.
• Architect ADCs (column-parallel, SAR, Sigma-Delta) for readout architectures.
• Optimize power consumption using subthreshold design, duty-cycling, and power gating.
• Collaborate with physical design on layout, matching, shielding, parasitics.
• Support silicon bring-up, characterization, and debugging in lab.

Skills

LNA design

ADC design (column-parallel)

deep sub-micron CMOS

Cadence tools (Spectre, Virtuoso, Cal

Education

Bachelor’s/Master’s/Ph.D. in Electrical Engineering

Tools

Cadence tools (Spectre, Virtuoso, Calibre)

Job description

Job Title: Senior Analog Circuit Design Engineer

Experience: 5+ Years

Employment Type: Full-time

Role Overview:

We are seeking an experienced Analog IC Design Engineer to join our design team. In this role, you will lead the architecture, design, and silicon validation of high-performance analog and mixed-signal blocks. You will be instrumental in building readout circuits for advanced sensor platforms, emphasizing low-noise signal conditioning, high-density data conversion, and ultra-low-power operation.

Key Responsibilities:

• Circuit Architecture & Design: Own the end-to-end design lifecycle (from specification to tape-out) for ultra-low-power Analog IC blocks.
• Low-Noise Frontend: Design high-precision Low-Noise Amplifiers (LNAs), programmable gain amplifiers (PGAs), and bandgap references tailored for low-amplitude sensor signal extraction.
• Data Converters: Architect and implement high-efficiency ADCs, specifically focusing on column-parallel ADCs for sensor readout architectures, SAR ADCs, or Sigma-Delta topologies.
• Power Optimization: Implement cutting-edge, ultra-low-power circuit strategies (subthreshold design, duty-cycling, power gating) to maximize energy efficiency for edge-sensing applications.
• Silicon Implementation & Layout: Collaborate closely with physical design engineers on analog layout, matching, shield strategy, parasitic extraction, and floorplanning to mitigate noise and crosstalk.
• Silicon Validation: Support silicon bring-up, characterization, and debugging in the lab using high-precision test equipment.

Qualifications & Requirements

Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Microelectronics, VLSI Design, or a related field and 12-15 years of experience

Core Expertise:

• Proven experience in Low-Noise Amplifier (LNA) design and noise optimization techniques (flicker noise reduction, thermal noise budget management).
• Direct experience designing ADCs, with strong preference for column-parallel ADC architectures used in array/imaging/sensing readout circuits.
• Demonstrated track record of ultra-low-power analog circuit design in deep sub-micron CMOS process nodes.
• EDA Tools: Hands-on proficiency with industry-standard cadence tools (Spectre, Virtuoso, Calibre, Monte Carlo analysis).
• Silicon Success: Preferred background of successfully taped-out ICs with verified laboratory silicon characterization.

What We Offer

• Collaborative culture working alongside industry veterans in image sensors and system architecture.
• Opportunity to build high-impact, semiconductor technology for critical global applications.
• Competitive compensation package including equity options.