Firmware Engineer-Lead

Mulya Technologies

Pune District

On-site

INR 4,000,000 - 7,000,000

Full time

2 days ago
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Job summary

Mulya Technologies is seeking a Firmware Engineer Lead based in Pune to drive embedded firmware development for PCIe-driven products. You will architect and implement firmware for high-speed data-center hardware and collaborate with SoC teams across PCIe, NVMe, and AMBA interfaces.

Ideal candidates have 12–20 years of experience in server/storage/networking firmware, with C/C++, Python automation, and hands-on experience with BMC and SDK development.

Qualifications

  • Experience developing embedded firmware for PCIe products.
  • Proficient in C (preferred) or C++, including SDK development.
  • Proficient in Python for automating pre/post processors.
  • Experience with gcc/Make, Doxygen, GitHub.
  • Hands-on with Server/Storage/Networking equipment.
  • Familiar with SoC interfaces (PCIe controllers, NVMe, AMBA/AHB).
  • Experience with high-speed data-center interfaces (PCIe Gen3+, 100/400G Ethernet, NVMe).

Skills

Embedded firmware
C/C++
Python
gcc/Make
Doxygen
GitHub
SoC interfaces
PCIe/NVMe
100/400G Ethernet
BMC / system mgmt

Education

Bachelor’s in EE or CS
Master’s preferred

Tools

Doxygen
GitHub

Job description

We are actively seeking a Firmware Engineer Lead, based in Pune.

https://www.thecube.net/events/nyse/ai-factory-data-center-of-the-future/content/Videos/d1ad8af3-1424-4336-a9b3-1d02b5a354b4

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems - a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency - unlocking unprecedented efficiency for AI training and inference at scale.

our architecture is not just an incremental improvement - it's a foundational shift in how AI hardware is built for the future.

We are actively seeking a Firmware Engineer Lead, based in Pune.
Required Experience:
  • Experience developing embedded firmware for PCIe products.
  • High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
  • High level of proficiency in Python for automating pre-processors/post-processors.
  • Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.
  • Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).
  • Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces
  • Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc
Preferred Experience:
  • Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC)
  • Experience with industry forums and collaboration workgroups such as OCP and OpenBMC
  • Experience with storage or SSD firmware, including NVMe, PCIe, CXL or flash management concepts.
  • Hands-on experience with simulation or virtual platform-based development (e.g., VDK, QEMU, or similar)
Qualifications:
  • Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
  • Minimum 12-20 years' (Lead/Architect) experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
  • Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).
  • Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
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