Firmware Architect

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Mulya Technologies is building cutting-edge AI infrastructure hardware with a focus on energy-efficient, high-bandwidth SerDes-based memory fabrics. We seek a Firmware Architect to lead silicon bring-up, define firmware architecture for 224G/lane retimers, and own FEC/telemetry pipelines for predictive telemetry.

The role requires 10+ years in embedded firmware for SerDes/retimer products, with experience in IEEE 802.3ck/dj link training and RTOS environments.

Qualifications

• 10+ years embedded firmware in high-speed SerDes/retimer products.
• Silicon bring-up as lead (first samples to production).
• IEEE 802.3ck and 802.3dj link training experience.

Responsibilities

• Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry).
• Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane).
• Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry.

Skills

C (C99)

Assembly

Python

CI/CD

Static analysis

Telemetry

Standards

SerDes

FEC

OSPF/OIF

Education

BS in Electrical Engineering / Computer Engineering / Computer Science

MS preferred, DSP/comms focus

Tools

Hardware-in-loop tests

RTOS (FreeRTOS/Zephyr)

Job description

https://www.thecube.net/events/nyse/ai-factory-data-center-of-the-future/content/Videos/d1ad8af3-1424-4336-a9b3-1d02b5a354b4

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

We are actively seeking a Firmware Architect either based in Hyderabad OR Bangalore.

Responsibilities

• Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry)
• Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane), including adaptation algorithms and fallbacks
• Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry
• Lead silicon bring-up, partnering with ASIC design and signal integrity
• Ensure standards compliance (IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP)
• Travel: Up to 15% (silicon bring-up, standards meetings)

Skills

• Good knowledge of C (C99, MISRA), assembly for critical paths, Python for tools
• Good knowledge of CI/CD, static analysis, hardware-in-loop tests
• Good understanding of standards implementation (IEEE 802.3, OIF)
• Good knowledge of SerDes architecture (equalization, telemetry, interrupts)
• Self-motivated, with strong sense of ownership and responsibility
• Good communication and reporting skills

Experience

• Principal / Senior Staff (10+ years post-degree)
• 10+ years embedded firmware in high-speed SerDes/retimer products
• Silicon bring-up as lead (first samples to production)
• IEEE 802.3ck and 802.3dj link training experience
• RTOS (FreeRTOS/Zephyr) on constrained MCUs (1MB flash, 256KB RAM)

Education

• BS in Electrical Engineering, Computer Engineering, or Computer Science (MS preferred, DSP/comms focus)

Skills

• DSP
• firmware
• zephyr
• 802.3
• PAM4
• FEC
• OIF
• AEC
• CMIS
• OSPF