Principal SOC Physical Verification & Integration Specialist

EnCharge AI, Inc.; India; Hybrid; INR 6,000,000 - 12,000,000; Full time

Job summary

EnCharge AI, Inc. in Bangalore seeks a Principal SOC Physical Verification & Integration Specialist to drive full-chip integration and tapeout of large-scale SOCs for edge-to-cloud AI hardware.

You will own the physical integration strategy from floorplan to signoff, coordinating with PD and STA to meet stringent PPA targets. Ideal candidates have 14–20 years of hands-on SOC design and verification experience, expert knowledge of RTL-to-GDSII flow, and proficiency with Cadence Innovus and

Qualifications

• 14-20+ years of hands-on SOC physical design and PV experience.
• Deep understanding of RTL-to-GDSII flow and PV challenges in flat vs hierarchical designs.
• Strong communication with PD and STA teams to ensure timing closure.

Responsibilities

• Drive full-chip physical assembly of very large-scale SOCs (multi-billion transistors).
• Manage top-level floorplanning, bump planning, PG integration, and top-level clock/routing integration.
• Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff with industry tools at advanced nodes.

Skills

RTL-to-GDSII flow

Physical integration

PV methodology

Top-level integration

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

Cadence Innovus

Siemens Calibre (nmDRC/nLVS/PERC)

Synopsys IC Validator

Job description

Principal SOC Physical Verification & Integration Specialist

www.EnchargeAi.com

The 10 Hottest Semiconductor Startups Of 2025 (So Far)

https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-far?page=11

Location : Bangalore ( Hybrid- 2days office, 3 days-home) / Remote

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Experience: 14-20 Years

Job Title: Principal SOC Physical Verification & Integration Specialist

Department: Silicon Engineering / Physical Design

Role Overview

We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA).

Key Responsibilities

• Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration.
• Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs.
• Signoff Execution & Debugging: Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below).
• Cross-Functional Collaboration: Partner tightly with the Physical Design (PD) and Static Timing Analysis (STA) teams. Proactively resolve integration conflicts—such as top-level routing congestion or interface timing violations—ensuring that physical fixes do not disrupt timing closure.
• Design Rule Co-Optimization: Work directly with foundry partners to interpret complex design rules and waive or resolve edge-case violations specific to reticle-limit designs.
• Automation & Flow Development: Develop robust scripts and utilities to automate physical integration tasks, database merging, and PV result parsing to accelerate the tapeout cycle.

Required Qualifications

• Experience: 14-20 + years of hands-on experience in SOC physical design and physical verification, with a proven track record of taping out very large, complex SOCs (e.g., Datacenter, AI accelerators, or high-performance Compute chips).
• Technical Domain Expertise: * Deep understanding of the entire RTL-to-GDSII flow, with expert-level knowledge of physical integration challenges in flat vs. hierarchical methodologies.
• Strong foundational understanding of Physical Design and Static Timing Analysis (STA) to effectively communicate with implementation teams and assess the timing impact of PV fixes.
• Tool Proficiency: * Mastery of top-level integration tools (Cadence Innovus).
• Expertise in physical verification suites (e.g., Siemens Calibre nmDRC/nLVS/PERC, Synopsys IC Validator).
• Familiarity with chip/package co-design and bump planning tools.
• Programming/Scripting: High proficiency in Tcl, Python, and/or Perl for EDA flow automation and database manipulation.
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

• Experience with multi-die integration, 2.5D/3D packaging, or chiplet-based architectures.
• Previous experience leading tapeout operations for start-up or fast-paced advanced technology environments.
• Advanced knowledge of custom layout integration and mixed-signal IP drop-in