Principal, IC Package Engineer

Jobtailor

Bengaluru

On-site

INR 4,000,000 - 7,000,000

Full time

14 days+

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Benefits offered by this job

Health insurance

Job summary

Jobtailor is seeking a senior package design engineer to lead high-speed routing and manufacturability for Microchip products. You will work on MCM packages, flip chip and wire bond designs, and collaborate with SI and reliability teams.

Provide input data for design flow, create routing constraints, oversee internal and external designers, and produce detailed reports and schedules for customer satisfaction and timely delivery.

Qualifications

Bachelor’s or Master’s degree in a related field.
10+ years of industry experience.
Expert in package design using Cadence APD.
Expert in authoring APD design rules.
Scripting in PERL or SKILL is an asset.
Familiarity with flip chip and wire bond package designs.
Familiarity with PCB design and BGA fanout issues.
Understanding of high speed and power routing rules.
Capable of handling multiple tasks at once.
Customer oriented, with attention to detail.

Responsibilities

Conduct package routing feasibility and substrate layouts for Microchip high-speed products.
Perform simple PCB breakout studies for ball map feasibility.
Identify key issues for proposed designs based on silicon floor plans and desired package sizes.
Work with signal integrity engineers to implement high speed signal routes and quiet power routes.
Work with reliability engineers and external vendors to ensure manufacturability of package designs.
Create package routing constraints based on signal integrity routing rules.
Interact with and oversee work of external and internal package designers.
Produce package routing reports and diagrams for review by external teams.
Create and track package design schedules.
Guide and assist external design teams on creation of input data for package design flow.

Skills

Package Design

Signal Integrity Routing

Scripting in PERL

Scripting in SKILL

PCB Breakout Studies

Flip Chip Design

Wire Bond Design

BGA Fanout Issues

Design Schedule Management

Education

Bachelor’s Degree

Master’s Degree

Tools

Cadence APD

Job description

Conduct package routing feasibility and substrate layouts for Microchip high-speed products, including MCM packages
Perform simple PCB breakout studies for ball map feasibility
Identify key issues for proposed designs based on silicon floor plans and desired package sizes
Work with signal integrity engineers to implement high speed signal routes and quiet power routes
Work with reliability engineers and external vendors to ensure manufacturability of package designs
Create package routing constraints based on signal integrity routing rules
Interact with and oversee work of external and internal package designers
Produce package routing reports and diagrams for review by external teams
Create and track package design schedules
Guide and assist external design teams on creation of input data for package design flow.

Requirements

Applicable Bachelor’s or Master’s Degree
10+ years of industry experience
Expert in package design using Cadence APD
Expert in authoring APD design rules
Scripting in PERL or SKILL is an asset
Familiarity with flip chip and wire bond package designs
Familiarity with PCB design and BGA fanout issues
Understanding of high speed and power routing rules/issues
Capable of handling multiple tasks at once
Customer oriented, with attention to detail

Core Competencies

Demonstrates expertise in package design, particularly using Cadence APD, with a strong focus on high-speed signal routing and manufacturability. Capable of managing complex design schedules and collaborating with internal and external teams to ensure design integrity and customer satisfaction.

Hard Skills