Principal Engineer, Design Verification

Mulya Technologies; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Mulya Technologies in Bengaluru seeks a senior design verification lead to drive pre-silicon verification for complex SoCs and subsystems. You will define verification strategy, build DV flows, and mentor a team across architecture, design, emulation, and software groups to ensure top quality deliverables.

Responsibilities include leading end-to-end verification of multi‑core processors, AI accelerators, and high-speed interfaces, developing scalable UVM testbenches, formal verification, and

Qualifications

• B.Tech/M.Tech with 12+ years in digital pre-silicon verification across IP, subsystem or SoC DV.
• Strong understanding of SoC architectures with hands-on Verilog/SystemVerilog and UVM.
• Proven track record in verification closure using functional and code coverage metrics.
• Expertise in NoC, interconnect verification and DV flows.

Responsibilities

• Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.
• Verify microprocessor-based designs, AI accelerators, and high-speed peripherals using advanced methods.
• Define and drive team execution with task planning, progress tracking, and mentoring.
• Collaborate with architecture and design to define requirements and deliverables.
• Drive pre-silicon readiness with emulation, FPGA and software teams for post-silicon validation.
• Develop end-to-end system-level use cases for functional validation.
• Architect and implement scalable UVM testbenches and DV flows.
• Define test plans and ensure coverage closure across blocks/SoC levels.
• Work cross-functionally with emulation, firmware, and system teams for full-system correctness.
• Apply formal verification techniques for IP and subsystem validation.
• Lead NoC/interconnect verification and robust data flow across SoC.
• Perform performance verification and system-level analysis on real use cases.
• Drive innovation in verification strategies to meet schedules and quality goals.

Skills

Verilog/SystemVerilog

UVM

SoC DV

NoC verification

Power-aware verification

Formal verification

C/C++

Python scripting

Testbench architecture

Education

B.Tech/M.Tech in ECE/EE/CS

Tools

GLS

Emulation

FPGA

Job description

Top20 Semiconductor Organization in the world

We are a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. combine analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $10 billion in FY25, we ensure today's innovators stay Ahead of What's Possible.

About the Role

Lead design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.

Responsibilities

• Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.
• Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.
• Define and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.
• Collaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.
• Drive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.
• Develop and execute end-to-end system-level use cases for comprehensive functional validation.
• Architect and implement scalable UVM-based testbenches, DV flows, and methodologies.
• Define and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels.
• Work cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.
• Apply formal verification techniques for IP and subsystem-level validation.
• Lead NoC/interconnect verification and ensure robust data flow across the SoC.
• Perform performance verification and system-level analysis across real-world use cases.
• Drive innovation in verification strategies to meet aggressive schedules and quality goals.
• Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.

Requirements

• B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.
• Strong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.
• Proven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.
• Expertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.
• Experience in architecting scalable testbench environments and defining robust DV flows and methodologies.
• Strong background in power-aware verification (UPF), including power analysis and optimization.
• Hands-on experience with formal verification, including flow definition, connectivity, and functional property checking.
• Solid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.
• Experience in security and safety verification, ensuring compliance with secure design and functional safety requirements.
• Familiarity with gate-level simulations with timing annotation (GLS).
• Strong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.
• Good understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).
• Exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.
• Excellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.
• Strong problem-solving mindset with the ability to quickly learn and adopt new technologies

Why You'll Love Working Here

At you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.

Your expertise will shape the future of technology, and you’ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.