Physical Design Engineer, Lead Engineer Senior

Qualcomm; Hyderabad; Sur place; INR 4 500 000 - 7 500 000; Plein temps

Résumé du poste

Qualcomm India Private Limited is seeking an accomplished hardware physical design engineer to own complete PD flows from netlist to GDS2, including PV/PDN/STA closure, with emphasis on floorplanning, CTS and signoff checks.

The role requires expertise in low-power islands, voltage islands, and debugging congestion, using Innovus and Fusion Compiler, plus TCL/Perl/Python scripting for flow improvements and collaboration with global teams.

Qualifications

• Thorough knowledge of the ASIC designs Place and Route flow and methodology.
• Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure
• Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
• Strong background in debugging Congestion and CTS issues.
• Expertise in PnR tools (Innovus/Fusion compiler) and flow.
• Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
• Understand and implement improving existing methodologies and flows.
• Proficient in scripting languages (TCL,PERL,PYTHON).
• Self-starter and highly motivated
• To have working experience in global team environment.
• To be effectively communicate the status and issues of respective owned Tasks
• 8+ yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks

Responsabilités

• Lead PD ownership from netlist to GDS2 and ensure closure of PV/PDN/STA checks.
• Execute floorplanning, PNR, CTS and signoff checks with quality and timely delivery.
• Work with global teams to implement low-power methodologies and voltage islands.
• Debug congestion and CTS issues and optimize timing closure.
• Utilize P&R tools (Innovus, Fusion) and scripting (TCL/Perl/Python) to automate flows.

Formation

Bachelor's degree in CS/EE/Engineering

Master's degree in CS/EE/Engineering

PhD in CS/EE/Engineering

Outils

Innovus

Fusion Compiler

Description du poste

Job Area

Engineering Group, Engineering Group > Hardware Engineering

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Jd

• Thorough knowledge of the ASIC designs Place and Route flow and methodology.
• Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure
• Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
• Strong background in debugging Congestion and CTS issues.
• Expertise in PnR tools (Innovus/Fusion compiler) and flow.
• Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
• Understand and implement improving existing methodologies and flows.
• Proficient in scripting languages (TCL,PERL,PYTHON).
• Self-starter and highly motivated
• To have working experience in global team environment.
• To be effectively communicate the status and issues of respective owned Tasks
• 8+ yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks

Applicants

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