Physical Design Engineer, Lead Engineer Senior

QUALCOMM, Inc.; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Qualcomm India Private Limited in Hyderabad, India seeks an experienced hardware design engineer specializing in physical design to own floorplanning, PNR, CTS and signoff checks from netlist to GDS2.

The role requires 8+ years in PD, collaboration with global teams, and proficiency with Innovus and Fusion Compiler, plus TCL/Perl/Python scripting to improve flows. This is a senior, hands-on position offering impact across silicon implementation and signoff.

Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• OR Master''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Responsibilities

• Thorough knowledge of the ASIC designs Place and Route flow and methodology.
• Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure
• Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
• Strong background in debugging Congestion and CTS issues.
• Expertise in PnR tools (Innovus/Fusion compiler) and flow.
• Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
• Understand and implement improving existing methodologies and flows.
• Proficient in scripting languages (TCL,PERL,PYTHON).
• Self-starter and highly motivated
• To have working experience in global team environment.
• To be effectively communicate the status and issues of respective owned Tasks
• 8+ yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks

Skills

Physical design

Floorplanning

PNR

CTS

Signoff checks

Scripting (TCL/Perl/Python)

PD ownership

Education

Bachelor's degree in CS/EE/Engineering or related field

Master's degree in CS/EE/Engineering or related field

PhD in CS/EE/Engineering or related field

Tools

Innovus

Fusion Compiler

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• OR
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Description

• Thorough knowledge of the ASIC designs Place and Route flow and methodology.
• Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure
• Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
• Strong background in debugging Congestion and CTS issues.
• Expertise in PnR tools (Innovus/Fusion compiler) and flow.
• Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
• Understand and implement improving existing methodologies and flows.
• Proficient in scripting languages (TCL,PERL,PYTHON).
• Self-starter and highly motivated
• To have working experience in global team environment.
• To be effectively communicate the status and issues of respective owned Tasks
• 8+ yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks

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