Physical Design Engineer

Mulya Technologies; Bengaluru; On-site; INR 1,200,000 - 2,500,000; Full time

Job summary

Mulya Technologies seeks a Physical Design Engineer (2–4 years) to join a high-caliber startup focused on AI hardware and software for edge-to-cloud computing. The role emphasizes end-to-end RTL-to-GDSII ownership, floorplanning, placement, and power-aware design in cutting-edge nodes.

Ideal candidates come from top-tier universities (IIT/NIT/BITS or equivalent) and bring hands-on experience with Innovus, MCMM, and UPF/CPF-based low-power techniques.

Qualifications

• Education: B.Tech/M.Tech in Electrical/Electronics from a Top Tier University.
• Experience: 2–4 years in Physical Design within the semiconductor industry.
• Tool proficiency: Expertise in Innovus (preferred).
• Depth: MCMM closure, low-power techniques (UPF/CPF), physical verification.

Responsibilities

• End-to-End Ownership: RTL-to-GDSII, floorplanning, placement, CTS, routing, LVS/DRC/ERC.
• Performance: optimize PPA targets in 3nm or below nodes.
• STA: timing closure, signal integrity, crosstalk analysis, CPPR optimization.
• Power: IR-drop analysis and EM checks for robust power delivery.
• Innovation: develop AI/ML-based automation scripts for design flow.

Skills

RTL-to-GDSII

Floorplanning

Placement

CPPR optimization

AI/ML-based automation

Python/Tcl scripting

Education

B.Tech/M.Tech in Electrical/Electronics Engineering (Top Tier University)

Tools

Innovus

Python

Tcl

Job description

About Company:

We are hiring for organization which is leader in advanced AI hardware and software systems for edge-to-cloud computing. Its robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. It was launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Job Description:

Physical Design Engineer (2-4 Years Experience)

We are looking for a high-caliber Physical Design Engineer to join our fast-paced startup team. This role is designed for "top 1%" talent—engineers from tier-1 universities (IIT/NIT/BITS or equivalent) who possess a relentless "go-getter" attitude and the critical thinking skills required to solve complex, next-generation silicon challenges.

If you are eager to move beyond standard digital flows into the future of AI-driven automation, this is your playground.

Key Responsibilities

• End-to-End Ownership: Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC).


• Performance Optimization: Execute high-performance design closure focusing on PPA (Power, Performance, Area) targets in advanced process nodes ( 3nm or below)


• Static Timing Analysis (STA): Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and CPPR (Common Path Pessimism Removal) optimization.


• Power Integrity: Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery.


• Innovation: Develop and integrate AI/ML-based automation scripts to optimize the physical design flow and reduce turnaround time.

Qualifications & Requirements

• Education: B.Tech/M.Tech in Electrical/Electronics Engineering from a Top Tier University.


• Experience: 2–4 years of hands-on experience in Physical Design within the semiconductor industry.


• Tool Expertise: Expert-level proficiency in industry-standard tools (Preferred Innovus).


• Technical Depth: Strong understanding of multi-corner multi-mode (MCMM) closure, low-power design techniques (UPF/CPF), and physical verification.


• Mindset: A proven "go-getter" who is diligent, detail-oriented, and capable of taking complete ownership of blocks under tight deadlines.


• The "Plus": Proficiency in Python/Tcl and experience using AI/ML models for EDA tool automation or predictive PPA analysis.