MTS DRAM ASIC Architect

micron; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Micron Technology, Inc. seeks an experienced architect to drive the definition of next-generation DRAM products integrating advanced CMOS-based logic die technologies.

The role involves defining architectures that enhance DRAM with logic-die capabilities across LPDDR, DDR, and HBM, with responsibilities spanning I/O, reliability, and system-level integration. The successful candidate will lead cross-functional technical discussions, perform tradeoff analyses, and influence roadmaps for memory

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline with 5+ years of experience in semiconductor architecture, design, or system engineering.
• Experience in DRAM architecture, memory subsystem architecture, ASIC/SoC architecture.
• Understanding of DRAM architecture including command flows, timing behavior, bank architecture, refresh management, row hammer mitigation, reliability features, and memory subsystem operation.

Responsibilities

• Define next-generation DRAM + logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms to optimize performance, power, cost, reliability, and product differentiation.
• Identify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic-die implementations; perform architectural tradeoff analysis covering area, power, latency, yield, testability, reliability, and product scalability.
• Define scalable CMOS logic-die architectures and subsystem solutions using a combination of custom, semi-custom, and standard IP solutions.
• Architect high-performance interfaces between DRAM die and logic die, including command, data, clocking, synchronization, test, monitoring, and management paths.
• Identify emerging opportunities & influence roadmaps for advanced memory system capabilities.

Skills

DRAM architecture

Memory subsystem architecture

ASIC/SoC architecture

CMOS logic die

Cross-functional leadership

Tradeoff analysis

Strong analytical skills

Architectural documentation

Education

BS/MS/PhD in Electrical Engineering/Computer Engineering/CS

Tools

High-speed I/O

IP evaluation

Job description

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

DRAM ASIC Architecture

Role Overview

Micron is seeking an experienced architect to drive the definition of next-generation DRAM products incorporating advanced CMOS-based logic die technologies.

This role will help define how future DRAM products leverage advanced CMOS logic die technologies to enable higher levels of integration, observability, reliability, power efficiency, security, and system differentiation beyond what is achievable in conventional DRAM-only implementations. The architect will define architectures that leverage advanced logic die capabilities to complement and enhance DRAM functionality across LPDDR, DDR, HBM and future heterogeneous memory solutions.

The successful candidate will architect I/O, reliability, manageability, interface, test and system-enhancement functions. The role requires strong collaboration across DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system architecture teams.

Key Responsibilities

• Define next-generation DRAM + logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms - to optimize performance, power, cost, reliability, and product differentiation.
• Identify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic-die implementations; perform architectural tradeoff analysis covering area, power, latency, yield, testability, reliability, and product scalability.
• Define scalable CMOS logic-die architectures and subsystem solutions using a combination of custom, semi-custom, and standard IP solutions.
• Architect high-performance interfaces between DRAM die and logic die, including command, data, clocking, synchronization, test, monitoring, and management paths.
• Identify emerging opportunities & influence roadmaps for advanced memory system capabilities.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline with 5+ years of experience in semiconductor architecture, design, or system engineering.
• Experience in one or more of the following areas: DRAM architecture, memory subsystem architecture, ASIC/SoC architecture.
• Good understanding of DRAM architecture including command flows, timing behavior, bank architecture, refresh management, row hammer mitigation, reliability features, and memory subsystem operation.
• Exposure to high-speed I/O, PHY architectures, clocking systems, SI/PI considerations, power delivery, thermal design, and/or die-to-die interfaces.
• Demonstrated ability to lead cross-functional technical discussions, develop architectural proposals, and drive tradeoff-based decision making.
• Strong analytical and problem-solving skills.
• Ability to drive architecture tradeoff studies across multiple engineering disciplines.
• Excellent written and verbal communication skills.

Preferred Qualifications

• Experience with DDR5/DDR6, LPDDR5/LPDDR6, HBM, GDDR, or emerging memory technologies with strong understanding of memory protocols, timing architectures, memory training, calibration, and PHY design.
• Experience evaluating architectural tradeoffs across DRAM die, logic die, advanced packaging, and system-level implementations.
• Experience with die-to-die interconnect technologies including TSV-based architectures, hybrid bonding, 2.5D/3D packaging, stacked-die systems, and advanced memory integration.
• Strong knowledge of CMOS technologies, semiconductor device fundamentals, analog/mixed-signal circuit concepts, and memory interface design.
• Understanding of SI/PI, clocking, power delivery, thermal considerations, and heterogeneous integration challenges.
• Experience working with industry standards organizations, customers, or ecosystem partners related to memory technologies.
• Experience with HBM base die architectures, embedded controllers, advanced memory system features, RAS, security, or logic-die-based memory products.
• Proven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies
• Leverage AI tools to automate the tools and workflow
• Applying Artificial Intelligence in workflows to improve build efficiency

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brand