Senior AI/ML Hardware Architect, Google Cloud

Google Inc.; Bengaluru; On-site; INR 3,800,000 - 7,000,000; Full time

Job summary

Google is shaping the future of AI/ML hardware acceleration in Bengaluru, focusing on TPU architecture and integration within AI/ML systems. You will drive breakthroughs in custom silicon solutions powering Google's AI workloads.

You will work with a high-impact team across hardware and software to deliver scalable, high-performance accelerators, leveraging your expertise in microarchitecture, memory systems and low-precision numerics.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 8 years of architecture and micro-architecture experience in ML/graphics or networking ASICs.
• Experience with memory hierarchy on chip, memory controllers, HBM/DRAM technologies.

Responsibilities

• Develop architecture specifications for AI/ML roadmap including power/performance models.
• Own microarchitecture of compute blocks and collaborate with hardware/software teams for codesign.
• Evaluate silicon solutions for AI accelerator roadmap with vendor co-developments and chiplets.
• Create high performance hardware/software interfaces and coordinate with cross-functional teams.
• Identify and drive power, performance and area improvements and contribute to simulations tools.

Skills

ML hardware architecture

Networking ASICs

Memory hierarchy on chip

Education

Bachelors degree in EE/CE/CS

Masters or PhD preferred

Tools

C++

Python

Job description

Senior AI/ML Hardware Architect, Google Cloud

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in architecture and micro-architecture design of graphics or Machine Learning (ML) or Ethernet/ROCE/UAL/NVlink scaleup/out fabrics or managing Low Precision/Mixed Precision Numerics/Vector processors/DSP processors or experience architecting networking ASICs.
• Experience in memory hierarchy on chip fabrics, memory controllers, High Bandwidth Memory (HBM), and Dynamic Random-Access Memory (DRAM) technologies.

Preferred qualifications:

• Master's degree or PhD in Computer Engineering, Electrical Engineering, or equivalent practical experience.
• Experience working with software teams optimizing the hardware/software interface.
• Experience in performance analysis and modeling, defining and driving performance test plans.
• Experience in programming languages (e.g., C++, Python).
• Knowledge of arithmetic units, bus architectures, accelerators or memory hierarchies and high performance and low power design techniques and use of ML tools for building smarter tools.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an Senior AI/ML Hardware Architect, you will focus on the definition and path-finding for next-generation TPUs, specializing in one of the following: graphics, Machine Learning (ML), ethernet/ROCE/UAL/NVlink scale-up/out fabrics, management of low-precision or mixed-precision numerics, vector processors, DSP processors.

In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You will contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and evaluate quantitative and qualitative performance and power analysis.
• Own microarchitecture of compute blocks and subsystems and partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces.
• Evaluate different silicon solutions for executing Google’s data center Artificial Intelligence (AI) accelerator roadmap, components, vendor co-developments, custom designs and chiplets.
• Create high performance hardware/software interfaces and collaborate with software, verification, emulation, physical design, packaging and silicon validation stakeholders to ensure designs are complete, correct and performant.
• Identify and drive power, performance and area improvements for the modules owned and develop and contribute to the simulations tools.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.