Memory Layout Engineer

ACL Digital; Noida; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

ACL Digital is seeking a mid-senior level Team Lead to drive Memory Compiler layout development and verification. The candidate will be responsible for guiding junior team members, ensuring high-quality design, and collaborating with cross-functional teams in India and Korea. Ideal candidates should possess strong problem-solving and leadership skills alongside expertise in semiconductor processes.

Qualifications

• Experience in layout design and verification for Memory blocks.
• Familiarity with memory layouts and their various levels.
• Proficient in Cadence tools and layout automation.

Responsibilities

• Oversee Memory Compiler layout development and verification.
• Guide junior team members and ensure project delivery.
• Communicate effectively with engineering teams in India & Korea.

Skills

Problem-Solving

Leadership

Layout Fundamentals

Communication Skills

Floor Planning

Education

Bachelor's in Engineering or related field

Tools

Cadence Tools

Mentor Calibre

Job description

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Team Lead | Empowering Teams | Strategic Execution | Result-Oriented Leadership

• Experience : 3 to 8 years

Role and Responsibilities:

• Responsible for Memory Compiler layout development and verification.·
• Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·
• Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation.· Responsible for on-time delivery of block-level layouts with acceptable quality.· Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.·
• Guide junior team-members in their execution of Sub block-level layouts & review their work.·
• Contribute to effective project-management.·
• Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Qualification/ Requirements:

• Should be well familiar with various levels of memory layouts from custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, decoders.·
• Should have expertise in floor planning, power planning, block area estimation of memory designs or compliers.·
• Should be able to perform leaf cell layout development and physical verification.·
• Should have adequate knowledge of schematics, interface with circuit designer and CAD and process development team.·
• Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.·
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,· Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.·
• Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.·
• Should have leadership qualities and able to do multi-tasking as required.·
• Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.·
• Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
• Knowledge of Skill coding and layout automation is a plus.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Design

• Industries

  Semiconductor Manufacturing

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