Lead PSV Engineer - Memory subsystem - REQ_2933

Tessolve; Bengaluru; On-site; INR 2,800,000 - 4,200,000; Full time

Job summary

Tessolve in Bengaluru, India is seeking a senior Memory Subsystem Validation Lead to drive post-silicon validation efforts for LPDDR interfaces. You will craft validation strategies, test plans and coverage for memory controllers and PHY, and execute LPDDR4/LPDDR4X/LPDDR5/LPDDR5X testing including init, training, timing and functional tests.

Lead debugging across SoC, controller, firmware and board levels and work closely with hardware teams on memory architecture and integration.

Qualifications

• 8 to 12 years of experience in memory subsystem validation.
• Hands-on experience with LPDDR4/LPDDR4X/LPDDR5/LPDDR5X.
• Strong knowledge of Memory Controller architecture and DDR/LPDDR PHY.
• Post-silicon validation and silicon bring-up experience.
• Ability to read schematics and hardware specifications.

Responsibilities

• Lead and execute memory subsystem and LPDDR validation across post-silicon environments.
• Develop validation strategies, test plans, test cases and coverage for memory controllers, PHY and LPDDR interfaces.
• Perform LPDDR4/LPDDR4X/LPDDR5/LPDDR5X interface validation, including initialization, training, timing and functional testing.
• Validate different memory configurations, frequencies, data rates, channels, ranks and memory densities.
• Debug memory-related failures at SoC, controller, PHY, firmware and board level.
• Collaborate with hardware design teams to understand memory controller, PHY, clocking, reset, power and interface architecture.
• Review hardware design specifications, block diagrams, schematics and documentation.

Skills

Memory validation

LPDDR interface

Post-silicon validation

DDR/LPDDR PHY

Schematic reading

Tools

Oscilloscope

Logic analyzer

Job description

• Lead and execute Memory Subsystem and LPDDR validation activities across post-silicon environments.
• Develop validation strategies, test plans, test cases and coverage plans for memory controllers, PHY and LPDDR interfaces.
• Perform LPDDR4/LPDDR4X/LPDDR5/LPDDR5X interface validation, including initialization, training, timing and functional testing.
• Validate different memory configurations, frequencies, data rates, channels, ranks and memory densities.
• Debug memory-related failures at SoC, controller, PHY, firmware and board level.
• Work closely with hardware design teams to understand memory controller, PHY, clocking, reset, power and interface architecture.
• Review hardware design specifications, block diagrams, schematics and relevant design documentation.

Areas Of Re Sponsibility

• Lead and execute Memory Subsystem and LPDDR validation activities across post-silicon environments.
• Develop validation strategies, test plans, test cases and coverage plans for memory controllers, PHY and LPDDR interfaces.
• Perform LPDDR4/LPDDR4X/LPDDR5/LPDDR5X interface validation, including initialization, training, timing and functional testing.
• Validate different memory configurations, frequencies, data rates, channels, ranks and memory densities.
• Debug memory-related failures at SoC, controller, PHY, firmware and board level.
• Work closely with hardware design teams to understand memory controller, PHY, clocking, reset, power and interface architecture.
• Review hardware design specifications, block diagrams, schematics and relevant design documentation.

Experience

8 to 12 years of experience

• Strong experience in Memory Subsystem validation and debug.
• Hands-on experience with LPDDR4/LPDDR4X/LPDDR5/LPDDR5X
• Good understanding of Memory Controller architecture, DDR/LPDDR PHY, Read/write leveling, Memory channels, ranks and banks, ECC and memory error handling.
• Strong knowledge of post-silicon validation and silicon bring-up.
• Experience in debugging failures across hardware, firmware and software layers.
• Ability to read and understand schematics, block diagrams and hardware specifications
• Good understanding of system-level interfaces such as PCIe, USB, I2C, SPI, UART, JTAG, etc., is an added advantage.
• Understanding SoC and memory subsystem architecture.
• Understanding memory controller and PHY integration

Reading and analyzing schematics and board layouts.