Lead Logic Design for UALink IP/Subsystem Engineer

Astera Labs; Bengaluru; Sur place; INR 600 000 - 900 000; Plein temps

Résumé du poste

Astera Labs is seeking a Lead Logic Design Engineer for UALink IP/subsystems in Bengaluru. The role focuses on RTL/microarchitecture development for high-bandwidth, low-latency interconnects and scalable architectures, driving optimization across performance, area, and power.

You will translate protocol requirements into precise microarchitecture, design robust control/data paths, and collaborate with verification, SoC, and physical design teams while mentoring engineers and supporting silicon

Qualifications

• Proficient RTL and microarchitecture expertise for UALink IP/subsystems.
• Experience with high-speed interconnects and data movement.
• Strong knowledge of flow control, arbitration, and buffering.
• Excellent SystemVerilog/Verilog coding and review skills.
• Experience with CDC, lint, synthesis, and timing analysis.
• Proven debugging, leadership, and mentoring abilities.

Responsabilités

• Lead UALink IP/subsystem RTL development.
• Translate protocol requirements into detailed microarchitecture.
• Design high-performance control and data-path logic.
• Work on buffering, arbitration, flow control, ordering, and error handling.
• Develop and review SystemVerilog RTL.
• Drive performance, area, power, and latency optimization.
• Collaborate with verification, SoC integration, and physical design teams.
• Debug complex functional and integration issues.
• Review RTL and mentor engineers.
• Support silicon debug and issue resolution.

Connaissances

RTL/microarchitecture

High-speed interconnects

Data movement & buffering

SystemVerilog/Verilog

CDC, lint, synthesis & timing

Debugging & leadership

Description du poste

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Lead Logic Design Engineer – UALink IP/Subsystem

Experience

6–10years

Job Summary

Lead RTL and microarchitecture development forUALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.

Key Responsibilities

• LeadUALinkIP/subsystem RTL development.
• Translate protocol requirements into detailed microarchitecture.
• Design high-performance control and data-path logic.
• Work on buffering, arbitration, flow control, ordering, and error handling.
• Develop and reviewSystemVerilogRTL.
• Drive performance, area, power, and latency optimization.
• Collaborate with verification, SoC integration, and physical design teams.
• Debug complexfunctionaland integration issues.
• Review RTL andmentorengineers.
• Support silicon debug and issue resolution.

Required Skills

• Strong RTL and microarchitecture experience.
• Experience with high-speed interconnects.
• Strong understanding of data movement, flow control, arbitration, and buffering.
• ExcellentSystemVerilog/Verilog skills.
• Experience with CDC, lint, synthesis, and timing.
• Strong debugging and technical leadership skills.

Preferred

• Direct UALink experience.
• Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
• Experience with AI/accelerator or high-performancecompute SoCs.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.