Lead Logic Design for UALink IP/Subsystem Engineer

Astera Labs; Bengaluru; On-site; INR 3,000,000 - 4,500,000; Full time

Job summary

Astera Labs is seeking a Lead Logic Design Engineer for UALink IP/subsystems in Bengaluru. You will lead RTL and microarchitecture development focused on high-bandwidth, low-latency interconnects, driving performance and area optimization.

The role requires strong RTL skills, experience with high-speed interconnects, and leadership to mentor engineers across verification and physical design teams. Collaborative, hands-on design work is essential.

Qualifications

• Strong RTL and microarchitecture experience.
• Experience with high-speed interconnects.
• Understanding of data movement, flow control, arbitration and buffering.
• Experience with CDC, lint, synthesis and timing.
• Strong debugging and technical leadership skills.

Responsibilities

• Translate protocol requirements into microarchitecture.
• Design high-performance control and data-path logic.
• Work on buffering, arbitration, flow control, ordering and error handling.
• Develop and review SystemVerilog RTL.
• Drive performance, area, power and latency optimization.
• Collaborate with verification, SoC integration and physical design teams.
• Debug complex functionality and integration issues.
• Review RTL and mentor engineers.
• Support silicon debug and issue resolution.

Skills

RTL design

Microarchitecture

High-speed interconnects

CDC & timing

Technical leadership

Tools

SystemVerilog

Job description

Lead Logic Design for UALink IP/Subsystem Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Lead Logic Design Engineer – UALink IP/Subsystem

Experience

6–10years

Job Summary

Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.

Key Responsibilities

• Translate protocol requirements into detailed microarchitecture.
• Design high-performance control and data-path logic.
• Work on buffering, arbitration, flow control, ordering, and error handling.
• Develop and review SystemVerilogRTL.
• Drive performance, area, power, and latency optimization.
• Collaborate with verification, SoC integration, and physical design teams.
• Debug complex functionality and integration issues.
• Review RTL and mentor engineers.
• Support silicon debug and issue resolution.

Required Skills

• Strong RTL and microarchitecture experience.
• Experience with high-speed interconnects.
• Strong understanding of data movement, flow control, arbitration, and buffering.
• Experience with CDC, lint, synthesis, and timing.
• Strong debugging and technical leadership skills.

Preferred

• Direct UALink experience.
• Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
• Experience with AI/accelerator or high-performance compute SoCs.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.