Lead IP Block level Verification Engineer

AMD; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

A leading semiconductor company is seeking an MTS Silicon Design Engineer in Hyderabad, India. The ideal candidate will lead the verification of complex designs using UVM and System Verilog, with a strong understanding of digital design verification. Candidates should have over 8 years of experience in relevant fields. The position offers competitive benefits and an inclusive work environment.

Qualifications

• 8+ years of experience in verification of digital designs.
• Strong understanding of ASIC and full custom chip development.
• Experience in verifying protocols like AXI3/4, DDR4/5, HBM, PCIe.

Responsibilities

• Lead and plan verification of complex digital design blocks.
• Create a comprehensive verification testplan with architects.
• Design and architect testbenches in System Verilog and UVM.

Skills

UVM

System Verilog

Verification techniques

Analytical skills

Problem-solving

Communication skills

Education

Bachelors or Masters in computer engineering/Electrical Engineering

Tools

Synopsys VCS

Cadence IES

Job description

MTS SILICON DESIGN ENGINEER

The Role

The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network‑On‑Chip (NOC) IPs, subsystems and SOC designs.

The Person

You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

• Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
• Interact with architects and design engineers to create a comprehensive verification testplan
• Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
• Create and enhance constrained‑random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
• Debug tests with design engineers to deliver functionally correct design blocks
• Identify and write coverage measures for stimulus quality improvements
• Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

Preferred Experience

• Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
• Strong understanding of state of the art of verification techniques, including assertion and coverage‑driven verification.
• Strong understanding of different phases of ASIC and/or full custom chip development is required.
• Experience in block level NOC (Net work on Chip) verification is a plus.
• Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
• Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus.
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
• Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
• Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC‑Formal, Magellan) is a plus.

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp

Benefits

Benefits are described at: AMD benefits at a glance.

Equal Opportunity

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.