ASIC Design Verification Engineer – Graphics

Advanced Micro Devices, Inc.; Madhapur; On-site; INR 1,400,000 - 2,100,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD is seeking an MTS Silicon Design Engineer to plan, build, and execute verification for graphics processor IP, aiming for bug-free final designs. You’ll collaborate across architects, hardware, firmware, and software drivers, and develop tests and test environments.

You’ll drive test plans, estimate effort, and debug failures with RTL and firmware teams, applying UVM and SystemVerilog while leveraging Linux/Windows environments.

Qualifications

• Proficient in IP level ASIC verification.
• Strong debugging skills for firmware and RTL using simulation tools.
• Experience with UVM testbenches and Linux/Windows environments.
• Proficient in Verilog, SystemVerilog, C, and C++.
• Graphics pipeline knowledge.
• Developing UVM based verification frameworks and testbenches, processes and flows.
• Automating workflows in a distributed compute environment.
• Exposure to SystemC and TLM with related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset.
• Desirable: video codec system or multimedia exposure.

Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand features to be verified.
• Build test plan documentation accounting for interactions with features, hardware, firmware, and software driver use cases.
• Estimate the time required to write new feature tests and required test-environment changes.
• Build directed and random verification tests.
• Debug test failures to determine root cause; work with RTL and firmware engineers to resolve defects.
• Review functional and code coverage metrics and adjust tests to meet coverage requirements.

Skills

ASIC verification

RTL debugging

UVM testbenches

Verilog/SystemVerilog

C/C++

Graphics pipeline

UVM framework development

Automation scripting

Leadership experience

SystemC/TLM

Education

Bachelor's or Master's degree in computer engineering/Electrical Engineering

Tools

Linux

Windows

Makefile

Shell scripting

Perl

Ruby

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re redesigning next‑gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward. Join us and, together, we’ll advance your career.

MTS SILICON DESIGN ENGINEER

THE ROLE:

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environment
• Experienced with Verilog, System Verilog, C, and C++
• Graphics pipeline knowledge
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Good working knowledge of SystemC and TLM with some related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset
• Desirable assets with prior exposure to video codec system or other multimedia solutions.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-PK2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.