Lead Engineer/ Staff – RISCV Subsystem RTL Design

Qualcomm; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Qualcomm India Private Limited in Bangalore seeks an experienced Hardware Engineer to own micro-architecture, RTL design, integration and delivery of RISC‑V subsystem components for next-generation SoCs across mobile, automotive, AI, compute and connectivity platforms.

The role requires strong VLSI design expertise, proficiency in Verilog/SystemVerilog, and collaboration with architecture, firmware, and verification teams to enable subsystem bring-up and post-silicon debug.

Qualifications

• Own micro-architecture, RTL design, integration and delivery of RISC-V subsystem components.
• Collaborate with architecture, software, verification and SoC teams to define requirements, interfaces, memory maps, interrupt architecture, power features, and subsystem integration strategies.
• Implement high-quality RTL using Verilog/SystemVerilog and drive design convergence through lint, CDC/RDC, synthesis, power intent, DFT, and formal verification checks.

Responsibilities

• Work with architecture, software, verification, and SoC teams to define requirements, interfaces, memory maps, interrupt architecture, power features, and subsystem integration strategies.
• Develop scalable micro-architecture specifications optimized for performance, power, area, safety, and product-specific use cases across multiple SoC programs.
• Implement high-quality RTL using Verilog/SystemVerilog and drive design convergence through lint, CDC/RDC, synthesis, power intent, DFT, and formal verification checks.
• Collaborate with firmware, verification, and integration teams to enable subsystem bring-up, feature validation, performance tuning, and seamless deployment into complex SoC environments.
• Debug and resolve functional, integration, timing, power, and silicon issues using simulation, waveform analysis, emulation, and post-silicon debug techniques.
• Drive technical reviews, mentor junior engineers, contribute to subsystem roadmap planning, and coordinate execution across globally distributed cross-functional teams.

Skills

VLSI design

RISC-V arch

Interrupt handling

Power management

Debug infra

AXI/AMBA interconnect

Scripting (Python)

ASIC flow

Team collaboration

Education

Bachelor's degree in Electronics/EE

Master's degree in related field

PhD in related field

Tools

Verilog/SystemVerilog

Synthesis tools

DFT

CDC/RDC

Formal verification

Emulation

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Job Area Engineering - IP Design

Location: Bangalore

Educational Requirements

Bachelor/Master’s Degree in Electronics & Communication / Micro Electronics

Job Description

Own micro-architecture, RTL design, integration, and delivery of RISC‑V subsystem components for next-generation SoCs targeting mobile, automotive, AI, compute, and connectivity platforms. The subsystem includes control CPUs, interrupt management, security, power management, debug, and system infrastructure blocks.

Job Responsibilities

• Work with architecture, software, verification, and SoC teams to define requirements, interfaces, memory maps, interrupt architecture, power features, and subsystem integration strategies.


• Develop scalable micro-architecture specifications optimized for performance, power, area, safety, and product-specific use cases across multiple SoC programs.


• Implement high-quality RTL using Verilog/SystemVerilog and drive design convergence through lint, CDC/RDC, synthesis, power intent, DFT, and formal verification checks.


• Collaborate with firmware, verification, and integration teams to enable subsystem bring-up, feature validation, performance tuning, and seamless deployment into complex SoC environments.


• Debug and resolve functional, integration, timing, power, and silicon issues using simulation, waveform analysis, emulation, and post-silicon debug techniques.


• Drive technical reviews, mentor junior engineers, contribute to subsystem roadmap planning, and coordinate execution across globally distributed cross-functional teams.

Required Skillset

• Strong VLSI digital design experience with expertise in micro-architecture development and RTL implementation.


• Good understanding of RISC‑V architecture, interrupt handling, memory management concepts, power management, debug infrastructure, and system-level design principles.


• Knowledge of on-chip interconnect protocols such as AXI, AHB, APB, ACE, CHI, or equivalent high-performance SoC fabrics.


• Strong debugging, analytical, and problem-solving skills with the ability to root-cause complex hardware and integration issues.


• Good understanding of ASIC development flow including architecture, RTL design, synthesis, timing closure, verification, and silicon bring-up.


• Effective communication and collaboration skills to work across architecture, software, verification, physical design, and SoC teams.

Desired Skillset

• Experience with low-power design techniques including clock gating, power collapse, retention, isolation, voltage domains, and UPF-based design methodologies.


• Familiarity with interrupt architectures such as RISC‑V AIA/APLIC/IMSIC, system control processors, safety mechanisms, and subsystem infrastructure IPs.


• Proficiency in scripting languages such as Python, Perl, or Tcl for automation, flow development, and productivity improvements.


• Working knowledge of synthesis, DFT, CDC/RDC, formal verification, assertions, performance analysis, and system-level modeling.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.


• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.


• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

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