Lead Engineer Physical Design

Quest Global; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A renowned engineering services provider is seeking a Lead Engineer in Physical Design to own the implementation of complex, low power SoCs targeted for IOT and MCU markets. The ideal candidate should have 4-7 years of experience in implementing complex designs and a strong knowledge of Cadence tools like Innovus and Tempus. This full-time engineering role requires proficiency in physical design flow and hands-on experience with low power designs. The company emphasizes diversity and a culture where every voice matters.

Qualifications

• 4-7 years of experience implementing complex SoC designs from RTL to GDS.
• Hands-on experience with low power designs and multiple voltage islands.
• Ability to implement, update and improve scripts in the Physical Design flow.

Responsibilities

• Own the Physical Design Implementation including Synthesis, Floorplanning, Placement, CTS, and Routing.
• Work on Physical Design and Timing Closure of complex SoCs targeted for the IOT and MCU markets.
• Drive die area, performance, and power goals for hierarchical blocks.

Skills

Cadence tools

Low power designs

Automation

DFT related topics

TCL

Python

Perl

Tools

Cadence Innovus

Cadence Tempus

CAD tools

Job description

Lead Engineer Physical Design – Quest Global

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

• Need to have Cadence tools experience like Genus, Innovus & Tempus.
• Have worked in low power designs / multi voltage designs.
• Experience with automation.
• Understand DFT related topics.

Job Description

• Own the Physical Design Implementation: Synthesis, Floorplanning, Placement, CTS, Routing.
• This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.
• 4-7 years experience implementing complex SoC designs from RTL to GDS.
• Responsible to drive die area, performance, power goals for hierarchical blocks/Top.
• Work on various stages of physical design implementation which includes floorplanning, IO planning, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IR drop, physical verification checks.
• Deep understanding and hands‑on experience in implementing SOCs with multiple voltage islands, power islands and other power reduction techniques.
• Hands‑on experience with CAD tools such as Innovus, Tempus and Genus is a must.
• DFT experience would be a plus.
• P&R, STA, and sign‑off checks in sub‑micron technologies using Cadence toolchains is highly valued.
• Strong fundamental knowledge in low power designs.
• Implement, update and improve scripts used in the Physical Design flow with TCL, Python, and/or Perl.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Engineering and Information Technology

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe our company culture is the key to making a true difference in every industry we reach. Our teams invest time and effort into internal culture work, ensuring that all voices are heard. We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. Embracing our unique differences makes us better, and solving the world’s hardest engineering problems requires diverse ideas, perspectives, and backgrounds.