iRage - FPGA Engineer - VHDL/Verilog

Irage; Maharashtra; On-site; INR 1,500,000 - 4,000,000; Full time

Benefits offered by this job

Health insurance

Competitive salary

Paid vacation (few weeks)

Offsite events and outings

Performance-based bonuses

Knowledge sharing sessions

Gym membership contribution

Sports and recreation facilities

Job summary

iRage is seeking an FPGA Engineer to contribute to a greenfield FPGA implementation in Maharashtra. The role requires in-depth RTL coding using Verilog and SystemVerilog, with hands-on experience in PCI Express, high-speed Ethernet, memory interfaces, and timing closure.

Proficiency with Xilinx Vivado and simulation tools is essential. Qualified candidates will have strong C and Python skills, a practical approach to hardware design, and a track record of delivering fast, scalable FPGA

Qualifications

• Adept skills in Verilog, System Verilog, Vivado.
• Ownership of RTL coding in Verilog/VHDL or taking ownership of existing implementations.
• Networking packet processing (PCS, MAC, UDP, TCP/IP).
• Experience with PCI Express.
• Knowledge of cryptography concepts.
• Memory interface concepts.
• High speed Ethernet.
• Understanding of hardware design, timing and resource management.
• Expertise in simulation tools: Xilinx Simulator, Questa Sim.
• Ability to create fast, scalable hardware designs; optimizing Verilog/VHDL to reduce latency.
• Willingness to work with existing IPs or develop from scratch.

Skills

Verilog

SystemVerilog

Vivado

Verilog/VHDL

PCI Express

High Speed Ethernet

Memory Interface

Xilinx Simulator

Questa Sim

C programming

Python

Timing closure

Hardware design

Tools

Xilinx Simulator

Questa Sim

Job description

Role Summary

An FPGA Engineer at iRage will be a part of the greenfield FPGA implementation.

What We Are Looking For

• Adept skills in Verilog, System Verilog, Vivado.
• Work experience around actual RTL coding done in Verilog/VHDL or at the least has picked up ownership of something already implemented :
• Networking packet processing projects like PCS, MAC, UDP, TCP/IP
• PCI Express
• Cryptographics
• Memory Interface
• High Speed Ethernet
• Understanding of hardware design, meeting timing and resource management.
• Expertise in simulation tools (Xilinx Simulator, Altera Questa Sim).
• Ability to create and implement a hardware design which is fast and scalable.
• Experience in optimizing Verilog/ VHDL code and reducing latency.
• An attitude to take the challenge to get something going using existing IPs or develop something totally from scratch.

Required Skillset

• Minimum 5 years of experience.
• Expertise in achieving timing closure.
• Experience in latest XILINX FPGA Architecture will be a plus.
• Knowledge on C programming.
• High level proficiency in Python.

Benefits

• We work hard. Period.
• We also value quality of life. Our cubicle free workplace and informally clad workforce reflects this.
• Competitive salary.
• Few weeks of paid vacation.
• Interaction and collaboration with global experts.
• Annual out-station offsite(s) and frequent outings.
• Multiple performance-based bonuses.
• Health insurance.
• A fun work environment with dedicated sports and recreation facilities.
• Opportunities to learn and lead: Frequent Knowledge Sharing Sessions conducted by co-workers.
• Work-related and extra-curricular competitions at office.
• Gymnasium at office building: with equal contribution by the firm towards membership.

(ref:hirist.tech)