Senior IP Architect - Unified Intel Chassis Platform

Intel Technology India Pvt Ltd; Bengaluru; Hybrid; INR 3,000,000 - 5,200,000; Full time

Job summary

Intel Technology India Pvt Ltd in Bengaluru seeks a Senior IP Architect to lead architecture specs for Unified Intel Chassis IP components and subsystems. The role combines architecture definition with implementation awareness and performance ownership across platforms and networks.

You will build performance environments, drive closure with cross-functional teams, define QoS and routing strategies, and ensure scalable, power-optimized designs for high-bandwidth traffic.

Qualifications

• MS degree in CS/EE and 4+ years of relevant experience.
• Experience in SoC IP architecture for interconnect and subsystem design.
• Familiarity with AMBA protocols and high-bandwidth, low-latency systems.
• Ability to translate goals into architecture requirements and trade-offs.

Responsibilities

• Author architecture specifications for Unified Intel Chassis IP components.
• Ensure architecture is implementation-aware, scalable, and power-optimized.
• Drive platform performance analysis and closure, including bottleneck identification.
• Build and enhance platform performance environments, models, and benchmarking flows.
• Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic.
• Partner with system architectures, RTL/design, verification, firmware/software, and performance teams.

Skills

SoC IP architecture

AMBA AXI/CHI/APB familiarity

Arbitration algorithms

Platform performance modelling

Cross-functional collaboration

Performance targets trade-offs

Education

MS degree in CS/EE

Tools

AI tools

Job description

Senior IP Architect – Unified Intel Chassis (UIC) IP and Platform Architecture

Role Overview

We are looking for an architecture lead to define and drive architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. This role combines architecture definition with implementation awareness and performance ownership. The candidate will work on platform-level performance, including building performance environments and driving closure in partnership with system architects and cross-functional teams. Definition of platforms- From IP level performance modelling platforms (like modelling a routing algorithm, an arbiter policy et al) Then scaled to larger subsystem/soc level performance modelling platforms (like full soc network modelling) The performance evaluation setups must feed into architectural decisions driving scalable and performant design components.

Key Responsibilities

• Author architecture specifications for Unified Intel Chassis IP components and subsystem integration.
• Ensure architecture is implementation-aware, scalable, and power-optimized.
• Drive platform performance analysis and closure, including bottleneck identification and optimization.
• Build and enhance platform performance environments, models, and benchmarking flows.
• Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic.
• Partner with system architects, RTL/design, verification, firmware/software, and performance teams to align architecture with product goals.
• Define architecture trade-offs, assumptions, interfaces, and measurable success criteria.

UIC IP Scope

• UIC Coherent and Non-Coherent Fabric
• Protocol Adaptors for industry-standard protocols (AXI, CHI, CXL, UAL, etc.)
• Cache Controller IP
• MMU / IOMMU IP
• Clock, Reset, and Power Management IP
• Debug and Analytics IP
• Security and Access Management IP

Qualifications

Required Qualifications

• MS degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 4 or more years of relevant technical experience.
• Strong experience in SoC IP architecture for complex interconnect and subsystem design.
• familiarity with AMBA protocols, especially AXI, CHI, and APB.
• Experience arbitration and routing algorithms, end-to-end QoS, and high-bandwidth low latency, scalable designs.
• Hands-on experience with building platform environments which can be scaled to model small IP components to complete network model
• Ability to define architecture requirements, interface contracts, performance targets, and power/performance/area trade-offs.
• familiarly with AI tools to develop machine readable specification documents for spec2silicon fast and reliable execution
• Strong collaboration and communication skills across architecture and implementation teams.

Preferred Qualifications

• Experience with fabric-based scalable platforms across multiple markets or generations.
• Strong exposure to performance modelling, SystemC/TLM/UVM, simulation, and data-driven architecture tuning.
• Prior experience writing high-quality architecture specifications used by design and verification teams.
• Familiarity with security architecture and access control frameworks in SoC platforms.
• understanding of cache architecture and memory management/address translation MMU, IOMMU.

Success Profile

• Translates system goals into practical, scalable, implementation-ready architecture.
• Balances performance, power, area, and schedule constraints effectively.
• Brings strong technical depth while driving alignment across teams.
• Delivers architecture that enables first-time-right integration and faster performance closure.

Job Type

Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details such as work model, location or time type are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.