Infra IP Design Verification -Staff Engineer

Qualcomm; Dadri; On-site; INR 1,200,000 - 2,500,000; Full time

Job summary

Qualcomm India Private Limited is seeking a Design Verification Sr/Lead Engineer to drive end‑to‑end verification of complex IP designs, focusing on NOC verification. You will lead strategies, architect scalable UVM environments, and oversee testbench components while mentoring DV engineers.

The role requires hands-on SystemVerilog, UVM, and AMBA proficiency, with experience in NOC verification, constrained random testing, functional coverage, and SVA.

Qualifications

• Bachelor’s degree with 3+ years hardware engineering or related work experience.
• Master’s degree with 2+ years hardware engineering or related work experience.
• PhD with 1+ year hardware engineering or related work experience.
• Strong hands-on experience with SystemVerilog, UVM, and AMBA protocols.

Responsibilities

• Lead verification strategy, planning, and execution for IP/SoC subsystems.
• Architect and develop scalable UVM-based environments.
• Build and oversee testbench components (agents, scoreboards, monitors, sequences, coverage models).
• Drive coverage closure (functional + code) and signoff.
• Lead debugging and root-cause analysis across RTL and verification environments.
• Ensure smooth verification component integration.
• Mentor DV engineers through reviews and technical leadership.
• Manage and deliver concurrent projects with timelines and quality.

Skills

SystemVerilog

UVM

AMBA AXI/AHB/APB

NOC verification

Constrained random verification

Functional coverage

SystemVerilog Assertions

Debugging

Perl/Python

Verification integration & reuse

Education

Bachelor’s degree in CS/EE/related

Master’s degree in CS/EE/related

PhD in CS/EE/related

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross‑functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

We are looking for a Design Verification Sr Engineer / Lead Engineer to drive end‑to‑end verification of complex IP designs, with a focus on NOC verification. This role requires strong hands‑on expertise in SystemVerilog, UVM, and AMBA protocols, along with the ability to lead teams, manage multiple projects, and drive verification excellence.

Key Responsibilities

• Lead verification strategy, planning, and execution for IP/SoC subsystems
• Architect and develop scalable UVM‑based environments
• Build and oversee testbench components (agents, scoreboards, monitors, sequences, coverage models)
• Drive coverage closure (functional + code) and signoff
• Lead debug and root‑cause analysis across RTL and verification environments
• Ensure smooth verification component integration
• Mentor and guide DV engineers through reviews and technical leadership
• Manage and deliver concurrent projects with ownership of timelines and quality
• Collaborate across cross‑site and cross‑functional teams

Required Technical Skills

• Strong expertise in SystemVerilog and UVM
• Experience with AMBA protocols (AXI/AHB/APB)
• Proven experience in NOC verification
• Strong knowledge of:
  • Constrained random verification
  • Functional coverage
  • SystemVerilog Assertions (SVA)
• Strong debugging skills
• Scripting: Perl and/or Python
• Experience in verification integration and reuse
• Experience Band- 8-12 Years

Preferred Skills

• Exposure to coherency protocol verification
• Experience in SoC/interconnect verification
• Automation and regression optimization experience

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