Hiring: Emulation Engineers | Hyd | Mirafra Technologies

Mirafra; Hyderabad, Bengaluru; Hybrid; INR 1,800,000 - 3,200,000; Full time

Job summary

Mirafra in Hyderabad seeks a seasoned Emulation Model Build Engineer with GPU/graphics SoC expertise to drive emulation model development on ZeBu platforms.

You will enable full-chip GPU emulation for pre-silicon validation, performance validation, and software bring-up, handling large-scale design partitioning, memory-heavy workloads, high throughput, and cross‑functional collaboration with architecture, RTL, DV, and software teams. This role emphasizes automation of build and regression flows.

Qualifications

• Bachelor's or Master's in Electronics or Computer Engineering.
• 6–9 years of experience in SoC emulation or verification.
• Strong experience with Synopsys ZeBu and SystemVerilog/Verilog.
• Understanding GPU architecture and memory bandwidth.
• Experience in model build, debug flows, and synthesis constraints.

Responsibilities

• Build, compile, and deploy GPU SoC emulation models on ZeBu platforms.
• Partition large GPU subsystems and map to hardware resources.
• Optimize emulation for high bandwidth and concurrency.
• Debug RTL, compile/elaboration, and runtime failures.
• Enable GPU software stack bring-up including firmware and drivers.
• Collaborate with architecture, RTL, DV, and software teams.
• Drive performance tuning and runtime stability.
• Develop automation for build and regression flows.

Skills

GPU emulation

ZeBu

SystemVerilog/Verilog

GPU architecture

Model build & debug flows

Scripting (Python/Tcl/Shell)

Education

Bachelor's/Master's in Electronics / Computer Engineering

Tools

Synopsys ZeBu

Veloce

Palladium

Job description

Job Description: Emulation Model Build Engineer - GPU

Location: Hyderabad

We are looking for a seasoned Emulation Model Build Engineer with strong experience in GPU/graphics SoC environments to drive emulation model development on Synopsys ZeBu platforms. This role involves enabling full-chip GPU emulation for pre-silicon validation, performance validation, and software bring-up, with emphasis on large-scale design partitioning, memory-heavy workloads, and high-throughput execution. Exposure to Veloce and/or Palladium is an added advantage.

Key Responsibilities

• Build, compile, and deploy GPU SoC emulation models on Zebu platforms
• Perform design partitioning and mapping for large GPU subsystems including shader cores, compute units, memory controllers, and interconnect fabrics
• Optimize emulation for high bandwidth and concurrency-heavy workloads
• Debug issues across RTL, compile/elaboration phases, and runtime failures
• Enable GPU software stack bring-up including firmware, drivers, and kernel integration
• Support graphics and compute workloads (OpenGL, Vulkan, etc.)
• Collaborate with architecture, RTL, DV, and software teams
• Drive performance tuning and runtime stability
• Develop automation for build and regression flows

Required Qualifications

• Bachelor's/Master's in Electronics / Computer Engineering
• 6-9 years of experience in SoC emulation or verification
• Strong experience with Synopsys ZeBu and SystemVerilog/Verilog
• Understanding of GPU architecture (parallel pipelines, scheduling, caches, memory bandwidth)
• Experience in model build, debug flows, and synthesis constraints

Preferred Skills

• Experience in GPU subsystems like graphics pipelines or AI accelerators
• Exposure to Veloce and/or Palladium
• Knowledge of graphics APIs like Vulkan or OpenGL
• Linux/firmware bring-up experience
• Familiarity with memory subsystem debugging and performance bottlenecks
• Scripting in Python, Tcl, Shell, or Perl

Soft Skills

• Strong debugging mindset
• Ability to handle complex GPU designs
• Good collaboration skills
• Ownership and proactive attitude

Key Deliverables

• Stable and high-performance GPU emulation models
• Reduced compile/runtime turnaround time
• Efficient debug of GPU workloads
• Automated and scalable workflows

Comments for Suppliers: Looking for an emulation engineer well versed in zebu flows, with some exposure to initial debug triage on test failures.