Hardware Design Engineer -2290

Sunrise Biztech Systems; Bengaluru; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Bengaluru is seeking a Hardware Design Engineer with 3-5 years of experience to work on DFT/ATPG for next-generation SoCs. The role emphasizes creating high-quality test patterns and improving manufacturing test efficiency.

You will collaborate with Architecture, Design, and CAD teams, develop automation using Python/Tcl, and apply AI-assisted analysis to accelerate debug and coverage improvements.

Qualifications

• B.E./B.Tech./M.E./M.Tech. in Electrical or Electronics Engineering with DFT/ATPG experience.
• Experience with DFT architecture and ATPG for complex SoCs.
• Hands-on scripting in Python or Tcl.
• Knowledge of ATPG tools (Mentor Tessent/TK or equivalent).
• Experience with static timing analysis and timing closure.

Responsibilities

• Work with Architecture to understand DFT architecture and requirements.
• Interface with Design/Physical teams to ensure DFT rules and implementation guidelines are met.
• Generate high-quality manufacturing test patterns for stuck-at and transition fault models.
• Simulate and verify ATPG and LBIST patterns for sign-off readiness.
• Develop, enhance, and maintain automation scripts and reporting utilities for efficient DFT delivery.

Skills

DFT ATPG experience

ATPG tools

Python/Tcl scripting

Static timing analysis

Debug/diagnostics

Education

Electrical/Electronics Eng (B.E./B.Tech./M.E./M.Tech.) with DFT/ATPG

Tools

Mentor Tessent / TK

Python scripting

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position:Hardware Design engineer

Experience: 3-5 Years

Location: Bangalore

Full Time Employment/contractual

Role & responsibilities

Education: B.E./B.Tech./M.E./M.Tech. in Electrical or Electronics Engineering with relevant DFT / ATPG experience.

Top 3 Skills

• Relevant exp in DFT ATPG should be 3+
• Exposure to DFT architecture and design for complex SoCs.
• Good working knowledge of ATPG tools, including Mentor Tessent / TK or equivalent platforms.
• Exposure to static timing analysis and timing closure.
• Excellent hands-on debug ability and strong scripting skills.
• Experience building DFT reporting frameworks, coverage dashboards, or automated quality gates.

Secondary skills

JD

Recommended experience profile

B.E./B.Tech./M.E./M.Tech. in Electrical or Electronics Engineering with relevant DFT / ATPG experience.

Role Summary

As a key member of the Server SoC DFT team, the successful candidate will play a significant role in ensuring the quality of next-generation SoCs through structural DFT, ATPG, LBIST, and execution-focused automation. In addition to owning core ATPG deliverables, this engineer will be expected to improve the speed, quality, and repeatability of manufacturing test pattern generation, coverage review, and debug closure by using strong scripting, reporting frameworks, and selective AI-assisted analysis.

Primary Responsibilities

• Work closely with the Architecture team to understand DFT architecture and implementation requirements.
• Interface with Design teams to ensure DFT design rules and implementation guidelines are met.
• Partner with Physical Design teams to ensure correct DFT implementation and timing closure.
• Generate high-quality manufacturing test patterns for stuck-at and transition fault models using on-chip test compression techniques.
• Simulate and verify ATPG and LBIST patterns and support sign-off readiness.
• Analyze coverage loss mechanisms and work with cross-functional stakeholders to drive design changes that improve ATPG coverage.
• Support Product Engineering on pattern delivery, silicon bring-up, and post-silicon debug.
• Develop, enhance, and maintain scripts, reporting utilities, and execution checkers required for efficient DFT delivery.

AI and Automation Responsibilities

• Build and maintain Python/Tcl-based automation to remove repetitive manual work in coverage rollups, pattern-quality review, run tracking, and execution reporting.
• Use AI-assisted tools responsibly to accelerate log triage, failed-clock analysis, checklist consolidation, retargeting setup, and debug data summarization while independently validating output quality.
• Apply data-driven methods to identify high-impact opportunities in test-time reduction, pattern-count reduction, re-run avoidance, and queue-loss reduction.
• Partner with CAD and EDA vendor teams to evaluate, deploy, and operationalize vendor-provided AI capabilities in ATPG, diagnosis, debug, and reporting flows.
• Create reusable flow infrastructure, templates, and regression checks that can scale across programs rather than remaining one-off scripts.

Required Skills and Experience

• Exposure to DFT architecture and design for complex SoCs.
• Good working knowledge of ATPG tools, including Mentor Tessent / TK or equivalent platforms.
• Exposure to static timing analysis and timing closure.
• Excellent hands-on debug ability and strong scripting skills.
• Strong practical Python and/or Tcl capability for automation, data parsing, report generation, and flow gap closure.
• Ability to use AI-assisted engineering tools productively and responsibly for repetitive tasks, code scaffolding, data triage, and debug acceleration.
• Sound engineering judgment to review, validate, and correct AI-generated code, recommendations, or summaries before they are used in production flows.
• Good communication skills and ability to work effectively in a worldwide team environment.

Job Responsibilities / Day-to-Day Activities

Qualifications & Experiences

Preferred Qualifications

• Experience building DFT reporting frameworks, coverage dashboards, or automated quality gates.
• Experience applying analytics or AI to coverage debug, diagnosis review, test-time optimization, or retargeting efficiency.
• Exposure to silicon data analysis, tester-readiness metrics, or manufacturing test cost optimization.
• Experience working with CAD, EDA vendor, or internal automation teams to productionize new flow capabilities.
• Post-silicon bring-up and failure-debug experience.

Preferred candidate profile

Education: B.E./B.Tech./M.E./M.Tech. in Electrical or Electronics Engineering with relevant DFT / ATPG experience.