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Intel is seeking a GPU IP Integration Model Build Engineer in Bengaluru to perform functional verification model integration of graphics logic components and to define verification infrastructure and TFMs for functional design verification. You will work closely with cluster owners to integrate their code into the media IP, using Verdi, VCS, and UVM/OVM tools.
Applicants should hold a Master's degree in Electronics, CS, or Embedded Systems with 3–7 years of hands-on experience in pre-silicon
Job Description: Performs functional verification model integration of graphics logic components, including 3D graphics, media, to ensure design will meet specification requirements. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Closely work with different clusters owners and integrate their code into media IP.
Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations:
Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A Work Model for this Role This role will require an on‑site presence.
* Job posting details (such as work model, location or time type) are subject to change.
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