FVCTO - Formal Verification Engineer

Intel; Bengaluru; Hybrid; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Intel India is seeking an experienced Formal Verification Engineer to verify IP and SoC microarchitecture using formal methods, including model checking and equivalence checking. The role involves creating verification plans, abstraction models, and proofs, while collaborating with architects and RTL teams to ensure robust design verification.

The position supports a hybrid work model in Bengaluru with opportunities to advance verification methodologies and maintain the verification

Qualifications

• Minimum Qualifications: 2-18 years of experience in formal verification.
• Preferred Qualifications: BTech/MTech in Electronics, Electrical or CS.
• Requirements may be obtained through a combination of job experience, internships and/or schoolwork/classes/research.

Responsibilities

• Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.
• Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.
• Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.
• Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies.
• Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.
• Maintains and improves existing functional verification infrastructure and methodology.
• Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic.
• Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.

Skills

Formal verification

Model checking

Equivalence checking

BDD/DFG understanding

Education

BTech/MTech in Electronics, Electrical or CS

Tools

Model checking tools

Job description

• Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.
• Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.
• Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.
• Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies.
• Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.
• Maintains and improves existing functional verification infrastructure and methodology.
• Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic.
• Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.

Job Details

Job Description

• Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.
• Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.
• Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.
• Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies.
• Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.
• Maintains and improves existing functional verification infrastructure and methodology.
• Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic.
• Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Minimum Qualifications: 2-18 years of experience in formal verification
• Preferred Qualifications:
• BTech/MTech in Electronics, Electrical or CS
• Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.