Fpga Verification Engineer

Satus Smart Solutions; Hyderabad; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Satus Smart Solutions is seeking an FPGA Verification Engineer to join our avionics-focused team in Hyderabad. You will drive RTL verification, testbench development, and system validation for FPGA/SoC platforms, with emphasis on DO-254 compliance and safety-critical applications.

You will verify interfaces (AXI, UART, SPI, I2C), create verification environments, and collaborate with hardware and software teams to ensure robust hardware validation and regression testing.

Qualifications

• Experience in Verilog/SystemVerilog and RTL verification.
• Hands-on FPGA/Vivado experience.
• Knowledge of AXI protocols, digital design, CDC, timing, FSMs.
• Experience in simulation, waveform debugging, and coverage analysis.
• Proficiency in Python and Embedded C.

Responsibilities

• Develop verification testbenches using Verilog/SystemVerilog and UVM.
• Perform RTL functional verification, assertions, coverage, and regression testing.
• Verify AXI4/AXI4-Lite/AXI4-Stream, UART, SPI, I2C interfaces.
• Simulate and debug waveform using Vivado/QuestaSim/VCS.
• Support DO-254 compliance, test plans, and reports.
• Perform root-cause analysis, stress testing, and system-level validation.

Skills

Verilog/SystemVerilog

RTL Verification

UVM

FPGA/Vivado

AXI Protocols

Simulation & Debugging

Python

Embedded C

Debugging & Analysis

Tools

Vivado

QuestaSim

VCS

SpyGlass

ILA/VIO

Job description

Job Summary

We are looking for an FPGA Verification Engineer with experience in RTL verification, FPGA/SoC platforms, and safety-critical systems. The candidate will work on verification, debugging, system integration, and hardware validation for avionics applications.

Key Responsibilities

• Develop verification testbenches using Verilog/SystemVerilog and UVM.
• Perform RTL functional verification, assertions, coverage, and regression testing.
• Verify AXI4, AXI4-Lite, AXI4-Stream, UART, SPI, I2C and other interfaces.
• Perform simulation and waveform debugging using Vivado, QuestaSim, or VCS.
• Validate Zynq/SoC PS-PL integration, AXI transactions, registers, and interrupts.
• Perform Lint, CDC, Reset analysis using SpyGlass or similar tools.
• Support FPGA board bring-up and debugging using ILA/VIO.
• Develop verification automation using Python.
• Support DO-254 compliance, requirements traceability, test plans, procedures, and reports.
• Perform root-cause analysis, stress testing, fault injection, and system-level validation.

Required Skills

• Strong knowledge of Verilog/SystemVerilog, RTL Verification, UVM.
• Hands-on experience with FPGA/Vivado.
• Good understanding of AXI protocols, digital design, CDC, timing, and FSMs.
• Experience in simulation, waveform debugging, and coverage analysis.
• Knowledge of Python and Embedded C.
• Strong debugging and analytical skills.

Good to Have

• Aerospace/Avionics experience.
• Knowledge of DO-254.
• Experience with Zynq/Zynq UltraScale+.
• Knowledge of ARINC 429 / MIL-STD-1553.
• Exposure to SpyGlass, PCIe, Ethernet, or formal verification.