FPGA Design Technical Leader

Info Way Solutions; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Info Way Solutions in Bengaluru, India, seeks an experienced FPGA engineer to drive the design of complex data-path and control-path FPGAs. You will craft RTL specifications, write Verilog/VHDL/SystemVerilog, and validate designs to ensure bug-free RTL for first-pass success on boards.

You will collaborate with hardware, software, diagnostics, and signal integrity teams, mentor junior designers, and contribute to design methodology improvements.

Qualifications

• 7+ years of FPGA design experience required.

Responsibilities

• Design and implementation of FPGAs.
• Participate in the architecture definition, implementation and verification phases.
• Detailed design specification and test plan development.
• Develop and implement block level RTL, perform synthesis and achieve timing closure.
• Work with multi-functional teams (hardware, software, diagnostics and signal integrity groups).
• Assist in complex subsystem level lab bring-up, integration, and unit test validation.
• Contribution to the design process adoption within the team.

Skills

FPGA design

Verilog

VHDL

SystemVerilog

HDL design

FPGA timing

UVM

PCIe

Ethernet protocols

Vivado

Quartus

Libero

Education

MTech/BTech in EE/EC

Tools

Vivado

Quartus

Libero

Job description

We are part of the Common Hardware Group, with our team specializing in FPGA development. Our work spans both sophisticated data-path and challenging control-path FPGAs. The design process includes crafting the FPGA functional specification document, RTL coding, image generation and validation. We leverage industry-standard tools for FPGA design, incorporating various quality metrics to ensure a robust process. Our ultimate goal is to deliver bug-free RTL for first-pass success on the board. Additionally, we collaborate closely with our remote teams based in US and Italy.

Your Impact

• Design and implementation of FPGAs.
• Participate in the architecture definition, implementation and verification phases.
• Detailed design specification and test plan development.
• Develop and implement block level RTL, perform synthesis and achieve timing closure.
• Work with multi-functional teams (hardware, software, diagnostics and signal integrity groups).
• Assist in complex subsystem level lab bring-up, integration, and unit test validation.
• Contribution to the design process adoption with in the team.

Minimum Qualifications

• Educational Background: Requires 7+ years of experience in FPGA designs with MTech/BTech in EE/EC domain.
• Experienced in crafting with Xilinx, Altera and Microsemi FPGAs or Proficiency in HDL languages (Verilog, VHDL and System Verilog)
• Hands on experience with FPGA vendor tools like Vivado, Quartus and Libero
• Hands-on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc. Familiarity with simulation flow like UVM and VMM will be an added advantage.
• Basic knowledge on Unix system and script tool.
• Promote continuous improvement in design methodologies and processes
• Lead and mentor junior design engineers, offer technical guidance, and drive successful project execution
• Facilitates/encourages knowledge sharing in the team (e.g., brownbags, demos, design sessions).

Preferred Qualifications

• Knowledge on the signal integrity and system bring-up.
• Good English written and verbal communications. Self-motivation, partnership and strong interpersonal skills are needed.