Formal Verification Engineer, Sr Lead

Qualcomm; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Qualcomm India Private Limited is seeking a highly skilled Formal Verification Engineer with 6-8 years of hands-on FV experience to join the GCAD Formal team. You will drive verification of complex blocks, collaborate across global architecture, design and systems teams, and help strengthen sign-off quality.

The role demands strong scripting (Python preferred), expertise with formal tools such as Jasper, VC Formal and Questa Formal, and a willingness to innovate with low-power verification

Qualifications

• 5+ years of hands-on experience in Formal Verification.
• Strong understanding of formal concepts, proof strategies, and abstraction techniques.
• Proficiency with formal tools (Jasper, VC Formal, Questa Formal, etc.).
• Working knowledge of property-based FV (SVA) is a plus.
• Excellent scripting skills (Python strongly preferred).
• Strong analytical and problem-solving abilities.
• Clear communication skills and ability to collaborate with global teams.
• A strong willingness to learn, innovate, and deliver high-quality results.
• Low-power knowledge is a plus (UPF/CPF, isolation/retention, power/clock gating).

Responsibilities

• Drive formal verification of complex design blocks using Formal Apps and convergence strategies.
• Collaborate with worldwide architecture, design, and systems teams to achieve verification goals.
• Review and refine formal setups, proofs, constraints, and abstractions with design/DV teams.
• Engage with EDA vendors and evaluate advanced DV methodologies to improve sign-off quality.
• Develop automation scripts (Python preferred) to enhance FV flows.
• Analyze challenging formal problems and propose effective verification strategies.
• Low power formal methodology.

Skills

Formal verification

Python scripting

Analytical skills

Team collaboration

Education

Bachelor's degree in CS/EE

Master's degree in CS/EE

PhD in CS/EE

Tools

Jasper

VC Formal

Questa Formal

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Description

We are seeking a highly motivated Formal Verification Engineer with 6-8 yeas of experience to join our GCAD Formal team. The ideal candidate will have strong formal verification fundamentals, hands-on experience with formal tools, excellent analytical and scripting skills, and the ability to drive innovative verification methodologies. This role provides the opportunity to collaborate across global architecture, design, and systems teams to influence and strengthen verification sign‑off quality.

What You Will Be Doing

• Drive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies to achieve exhaustive and high‑confidence sign‑off.
• Collaborate with worldwide architecture, design, and systems teams to achieve verification goals.
• Review and refine formal setups, proofs, constraints, and abstractions with design/DV teams.
• Engage with EDA vendors and evaluate advanced DV methodologies to improve sign‑off quality.
• Develop automation scripts (Python preferred) to enhance efficiency and scalability of FV flows.
• Analyze challenging formal problems and propose effective verification strategies.
• Low power formal methodology

What We Need to See

• 5+ years of hands‑on experience in Formal Verification.
• Strong understanding of formal concepts, proof strategies, and abstraction techniques.
• Proficiency with formal tools (Jasper, VC Formal, Questa Formal, etc.).
• Working knowledge of property‑based FV (SVA ) is a plus.
• Excellent scripting skills (Python strongly preferred).
• Strong analytical and problem‑solving abilities.
• Clear communication skills and ability to collaborate with global teams.
• A strong willingness to learn, innovate, and deliver high‑quality results.
• Low‑power knowledge is a plus (e.g., power‑aware verification concepts, UPF/CPF, isolation/retention, power/clock gating, power‑aware apps, and basic power‑intent debugging).

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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