Field-Programmable Gate Arrays Engineer

Xeedo Technologies; Bengaluru; On-site; INR 600,000 - 1,000,000; Full time

Job summary

Xeedo Technologies in Bengaluru is seeking a hands-on FPGA engineer to design, develop, and verify high-speed digital systems for RF and DRFM applications.

You will work with Verilog/VHDL and Intel Quartus Prime, perform FPGA verification, and manage the full FPGA flow from RTL to timing closure.

Collaborate with RF, Embedded, Hardware, and System teams; contribute to hardware bring-up, validation, and documentation, ensuring robust, power-efficient designs.

Qualifications

• Design, develop, and implement FPGA-based solutions for RF, DRFM, and high-speed digital systems.
• Develop RTL using Verilog/VHDL and perform FPGA verification.
• FPGA development flow: RTL Design, IP Integration, Simulation, Synthesis, Place & Route, Timing Closure.

Responsibilities

• Design, develop, and implement FPGA-based solutions for RF, DRFM, and high-speed digital systems.
• Develop RTL using Verilog/VHDL and perform FPGA verification.
• Execute the complete FPGA development flow including RTL Design, IP Integration, Simulation, Synthesis, Place & Route, Timing Closure.
• Hardware bring-up, debugging, and system integration.
• Integrate vendor IPs such as DDR, Ethernet, PCIe, SPI, I2C, UART, PLL, and SerDes.
• Collaborate with RF, Embedded, Hardware, and System teams during product development.
• Develop and maintain FPGA design documentation and technical reports.
• Participate in design reviews and architecture planning.
• Optimize FPGA resource utilization, timing, and power.

Skills

Intel Quartus

Verilog/VHDL

FPGA timing

High-speed interfaces

DDR/PCIe

Board debugging

Signal processing

Education

BE/B.Tech in Electronics

Tools

QuestaSim

ModelSim

Job description

Experience: 2–8 Years

Employment Type: Full-Time

Key Responsibilities

• Design, develop, and implement FPGA-based solutions for RF, DRFM, and high-speed digital systems.
• Develop RTL using Verilog/VHDL and perform FPGA verification.
• Execute the complete FPGA development flow including:
• RTL Design
• IP Integration
• Simulation
• Synthesis
• Place & Route
• Timing Closure
• Hardware Bring-up and Debugging
• Integrate and customize vendor IPs including DDR, Ethernet, PCIe, SPI, I2C, UART, PLL, and SerDes.
• Perform FPGA simulation and debugging using QuestaSim/ModelSim or equivalent tools.
• Collaborate with RF, Embedded, Hardware, and System Engineering teams during product development.
• Support board bring-up,hardware validation, and system integration activities.
• Develop and maintainFPGA design documentation and technical reports.
• Participate in design reviews, technicaldiscussions, and architecture planning.
• Optimize FPGA resource utilization, timing performance, and power consumption.

Required Skills

• B.E./B.Tech/M.Tech in Electronics, ECE, EEE, or a related discipline.
• 3–5 years of hands-onFPGA development experience.
• Strong experience with:
• Intel Quartus Prime
• Proficiency in Verilog and/or VHDL.
• Strong understanding of FPGA implementation flow.
• Experience with FPGA timing constraints and timing closure techniques.
• Experience integrating vendor IPs and high-speed interfaces.
• Knowledge of DDR, PCIe, Ethernet, SPI, I2C, UART, and high-speed serial communication.
• Experience with board-level debuggingand hardware validation.
• Good understanding of digital design principles and signal processingconcepts.

Preferred Qualifications

• Experience in Defence, Electronic Warfare (EW), DRFM, Radar, SDR, or Satcom systems.
• Experience working on FPGA-basedsignal processing applications.
• Familiarity with high-speedtransceivers and SerDes architectures.
• Knowledge of TCL scriptingand FPGA design automation.
• Experience working with DRDO Labs, Defence PSUs (BEL, HAL, BDL), ISRO, or Defence R&D programs will be a strong advantage.

Location