Design Verification (GLS/Functional Ver) - Hyd Mirafra Technologies

Mirafra; Hyderabad; On-site; INR 1,200,000 - 1,600,000; Full time

Job summary

Mirafra Technologies in Hyderabad is seeking an experienced Design Verification Engineer to join our backend verification team. You will work on block- and IP-level verification using SystemVerilog/UVM to build robust testbenches and verification environments.

The ideal candidate has 3–8 years of experience in Functional Verification, a strong grasp of SystemVerilog/UVM, and hands-on experience with block/IP-level verification and SoC-level projects.

Qualifications

• Bachelor degree or higher in Electronics or related field.
• 3 to 8 years of experience in Functional Verification.
• Strong hands-on experience in SystemVerilog/UVM.
• Experience in block/IP-level verification.
• SoC-level experience is a plus.
• Excellent communication and ability to work independently.

Responsibilities

• Develop and maintain block-level testbenches using SystemVerilog/UVM.
• Create and execute verification plans (V-Plan), run regressions, and drive coverage closure.
• Work on testbenches with real number modeling.
• Perform netlist and gate-level simulations.

Skills

Functional Verification

Independent work

Excellent communication

Education

Bachelor's degree in Electronics

Tools

SystemVerilog/UVM

Testbench development

Real number modeling

Job description

Mirafra Technologies is Hiring!

Location: Hyderabad

Experience: 3 to 8 Years

Role: Design Verification Engineer

We are looking for experienced Functional Verification Engineers with strong expertise in SystemVerilog/UVM to develop and maintain block-level and IP-level verification environments.
The ideal candidate is proactive, self-driven, and capable of handling deliverables independently.

Key Responsibilities:

• Develop and maintain block-level testbenches using SystemVerilog/UVM
• Create and execute verification plans (V-Plan), run regressions, and drive coverage closure
• Work on testbenches with real number modeling
• Perform netlist and gate-level simulations

Qualifications & Experience:

• Bachelors degree or higher in Electronics or related field
• 510 years of experience in Functional Verification
• Strong hands-on experience in SystemVerilog/UVM
• Experience in block/IP-level verification
• Subsystem or SoC-level experience will be an added advantage
• Excellent communication and ability to work independently

If this sounds like you, we’d love to hear from you!