Design Verification Engineer AXI4/UVM

Sunrise Biztech Systems; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Part time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Hyderabad is seeking a Verification Engineer 3 for a 12-month contract.

The role focuses on SystemVerilog-based UVM functional verification and behavioral modelling of complex semiconductor blocks. You will perform system-level performance verification, traffic pattern analysis, AXI4/NOC protocol expertise, and contribute to testbench development and debugging across multi-master/multi-slave configurations.

Qualifications

• System Verilog based UVM Functional verification, Behavioral modelling of functional blocks.
• System level performance verification, traffic patterns, bandwidth & latency analysis.
• Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol.
• Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.
• Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.

Responsibilities

• Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera
• SV/UVM Functional verification
• Expertise in Vivado for simulation debugs

Skills

SystemVerilog

Functional verification

UVM

Tools

VCS

Questa

Xcelium

Riviera

Vivado

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you

Job Title: Engineering - Verification Engineer 3- 26-00511

Location: Hyderabad

Duration: 12 Months Contract

Job Description

System Verilog based UVM Functional verification, Behavioral modelling of functional blocks.

System level performance verification, traffic patterns, bandwidth & latency analysis.

Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol.

Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.

Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.

Basic Job Deliverable

• Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera
• SV/UVM Functional verification
• Expertise in Vivado for simulation debugs