Cryptographic Hardware Engineer

Felsite Technologies Private Limited; Ernakulam; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Felsite Technologies Private Limited is seeking a skilled engineer to advance post-quantum engine security. You will craft masking and countermeasures in SystemVerilog, aiming to withstand high-attack evaluators and validate protection at gate level on post-synthesis netlists.

The role emphasizes reading masking literature and applying rigorous RTL verification, with decisions on integration strategies and potential licensing. Kochi preferred, other locations possible for the right candidate.

Qualifications

• Proficient in synthesizable SystemVerilog and RTL basics.
• Able to read masking papers and reason about countermeasures.
• Experience with leakage verification at RTL/gate level preferred.

Responsibilities

• Raise side-channel protections on a post-quantum engine to withstand high-attack tests.
• Prove protection holds at gate level on post-synthesis netlist, not just RTL.
• Develop and integrate countermeasure RTL across the cryptographic subsystem.

Skills

SystemVerilog

Modular arithmetic

Finite fields

RTL tooling

Tools

RTL tooling

Job description

4–10 years. Kochi preferred; other locations considered for the right person. One seat.

One hard, bounded, genuinely interesting problem on a deadline that does not move: take our post-quantum engine to a side-channel posture that will stand up to a high-attack-potential evaluator, before the mask set freezes. It is fixed in silicon on tape-out day and does not get a second chance.

What you own

• Raising side-channel protection on our post-quantum engine to a level that stands up to a high-attack-potential evaluator. We have already accepted the die-area and schedule cost of doing that properly.
• Proving that protection holds at gate level on the post-synthesis netlist, not merely in RTL — a property upstream does not claim, and therefore ours to establish.
• Original countermeasure work where upstream leaves the algorithm exposed, and the patent filing that goes with it.
• Countermeasure RTL across the cryptographic subsystem — blinding, fault protection, temporal randomisation and supply-side hardening.
• Judging whether to integrate upstream’s own masking work, licence a commercial alternative, or sponsor the research. Your first deliverable is that judgement, not RTL.

What we look for

You write good synthesisable SystemVerilog, and you are comfortable enough with modular arithmetic and finite fields to read a masking paper and argue with it. That combination is the whole requirement.

What success looks like at twelve months

The mitigation path chosen and defended, the RTL written and integrated, and leakage-assessment results on a characterisation vehicle that say it worked — before the mask set closes.

What we fund

Masking theory — domain-oriented and threshold implementations, share-domain discipline, domain conversion. Post-quantum algorithms; the standards are three years old, so nobody has a decade of this. Gate-level leakage verification tooling, and sponsored research access at an Indian hardware-security lab.

Not required

A PhD. Prior post-quantum or side-channel experience. Publications. Ten years — four is fine if the four are strong. Any certification background; that is the other seat.