CPU Physical Design (RTL Feasibility)

NUVACORE; Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

Nuvacore is building high-performance, low-power CPU cores for next-generation compute workloads. As a CPU Physical Design (PD) Engineer, you will lead feasibility studies, drive PPA outcomes, and collaborate across multiple teams to ensure design readiness and timely tape-out.

Ideal candidates have strong µArch knowledge, RTL feasibility experience, and a track record of production tape-outs, with excellent communication skills to build scalable PD processes.

Qualifications

• BS or MS degree in EE, CS, or related field.
• 5+ years of CPU physical design experience for IC roles.
• 12+ years for Lead CPU PD roles.

Responsibilities

• Lead RTL/micro-architecture feasibility studies and provide actionable feedback to design teams.
• Drive PPA outcomes for CPU units with emphasis on timing closure and power optimization.
• Collaborate cross-functionally with CPU unit owners, CAD, RTL/micro-architecture, and performance modeling teams.
• Own the RTL intake process for the PD team and ensure design readiness before RTL handoff.

Skills

Micro-architecture

Timing analysis

RTL feedback

Cross-functional collaboration

Communication

Education

BS or MS degree

Tools

Synopsys

Cadence

Job description

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As physical design engineers focused on design feasibility you will focus on providing power, performance, and area feedback to the RTL team to ensure the design achieves all metrics and targets.

THE ROLE

As a CPU Physical Design (PD) Engineer, you will participate in the following :

• Lead RTL/micro-architecture feasibility studies, providing actionable feedback to design teams.
• Drive PPA outcomes for CPU units with a focus on timing closure and power optimization.
• Collaborate cross-functionally with CPU unit owners, custom circuit designers, CAD, RTL/micro-architecture, and performance modeling teams.
• Own the RTL intake process for the PD team, enforcing quality standards and ensuring design readiness before RTL handoff.

Minimum Qualifications

• Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design.
• Strong foundation in CPU micro-architecture (µArch) concepts and design principles.
• Experience in CPU RTL feasibility, including RTL synthesis and floor planning.
• Deep expertise in timing analysis and timing ECO.
• Proficiency with Synopsys or Cadence EDA tools for PD in CPU design context.
• Demonstrated history of successful production tape-outs.
• Track record of driving PPA optimization for CPU units through effective RTL feedback and cross-functional collaboration.
• Comprehensive understanding of end-to-end physical design closure across all sign off domains.
• Strong communication skills with the ability to build processes and infrastructure from the ground up

Requirements — Preferred

• Experience with some CPU units as block ownership taking from RTL to GDS (Tape-out).
• Proven track record in PPA optimization across CPU designs and EDA tooling
• Deep expertise in Physical Design (PD) sign off methodologies, including Formal Equivalence Verification (FEV), Voltage & Clock LP (VCLP), EM/IR analysis, Static Timing Analysis (STA), Extraction (EXT), and associated sign-off flows
• Proficiency in Python, Perl, and TCL for design automation and flow development.
• Experience in using Agentic AI tools for productivity and automation.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.