CPU Physical Design (RTL Feasibility )

NUVACORE; Bengaluru; On-site; INR 13,308,000 - 23,764,000; Full time

Job summary

NUVACORE in Bengaluru, India, is seeking a CPU Physical Design Engineer to drive PPA and timing closure while collaborating with RTL/micro-architecture teams to deliver high-performance, low-power CPUs for next-generation compute workloads.

The role includes leading RTL feasibility studies, owning the RTL intake process for PD, and working with design, CAD, and performance modeling teams to ensure design readiness and robust end-to-end sign-off across all domains.

Qualifications

• BS or MS in Electrical Engineering or related field.
• 12+ years for Lead roles or 5+ years for IC roles in CPU physical design.

Responsibilities

• Lead RTL/micro-architecture feasibility studies and provide feedback to design teams.
• Drive PPA outcomes for CPU units focusing on timing closure and power optimization.
• Collaborate with CPU unit owners, CAD, RTL/micro-architecture, and performance modeling teams.
• Own the RTL intake process for the PD team and ensure RTL handoff readiness.

Skills

CPU micro-architecture concepts

RTL feasibility

Timing analysis

PPA optimization

Cross-functional collaboration

RTL synthesis

Floorplanning

Signoff disciplines

Python/Perl/TCL

Tapeouts

Education

BS or MS in Electrical Engineering

Tools

Synopsys

Cadence EDA tools

Job description

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As physical design engineers focused on design feasibility you will focus on providing power, performance, and area feedback to the RTL team to ensure the design achieves all metrics and targets.

THE ROLE

As a CPU Physical Design (PD) Engineer, you will participate in the following :

• Lead RTL/micro-architecture feasibility studies, providing actionable feedback to design teams.

• Drive PPA outcomes for CPU units with a focus on timing closure and power optimization.

• Collaborate cross-functionally with CPU unit owners, custom circuit designers, CAD, RTL/micro-architecture, and performance modeling teams.

• Own the RTL intake process for the PD team, enforcing quality standards and ensuring design readiness before RTL handoff.

MINIMUM QUALIFICATIONS

• Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design.

• Strong foundation in CPU micro-architecture (µArch) concepts and design principles.

• Experience in CPU RTL feasibility, including RTL synthesis and floorplanning.

• Deep expertise in timing analysis and timing ECO.

• Proficiency with Synopsys or Cadence EDA tools for PD in CPU design context.

• Demonstrated history of successful production tapeouts.

• Track record of driving PPA optimization for CPU units through effective RTL feedback and cross-functional collaboration.

• Comprehensive understanding of end-to-end physical design closure across all signoff domains.

• Strong communication skills with the ability to build processes and infrastructure from ground up

REQUIREMENTS — PREFERRED

• Experience with some CPU units as block ownership taking from RTL to GDS (Tapepout).

• Proven track record in PPA optimization across CPU designs and EDA tooling

• Deep expertise in Physical Design (PD) signoff methodologies, including Formal Equivalence Verification (FEV), Voltage & Clock LP (VCLP), EM/IR analysis, Static Timing Analysis (STA), Extraction (EXT), and associated sign-off flows

• Proficiency in Python, Perl, and TCL for design automation and flow development.

• Experience in using Agentic AI tools for productivity and automation.

$140,000 - $250,000 a year