CPU Core Regression Debug Engineer

Tenstorrent; Bengaluru; On-site; INR 350,000 - 900,000; Full time

Benefits offered by this job

Competitive compensation

Equal opportunity employer

Job summary

Tenstorrent in Bengaluru, India, seeks a senior CPU verification engineer to own core-level regression, debug, and sign-off for the processor core. You will drive stimulus development, triage core-level failures, and coordinate with design and post-silicon teams to ensure high-quality delivery.

Experience with RTL, UVM-based stimulus, and simulators is essential. Proficiency in C/C++, Verilog/VHDL, Python, and scripting is required, along with strong knowledge of x86/ARM/RISCV ISAs.

Qualifications

• BS/MS/PhD in EE/ECE/CE/CS required.
• 7+ years of verified experience in CPU/IP validation or core verification.

Responsibilities

• Drive core level regression, debug, triage for core tests.
• Develop and refine stimulus for pre-silicon, emulation and post-silicon validation.
• Own bug hunting and propose configuration/coverage changes.
• Collaborate with design/test/post-silicon teams for high-quality deliveries.

Skills

C/C++

UVM stimulus

RTL DV debugging

Verilog/VHDL

Python scripting

PERL scripting

Waveform debugging

ISA knowledge

x86/ARM/RISCV

Emulation/Simulation

Education

BS/MS/PhD in EE/ECE/CE/CS

Tools

VCS

NC-Verilog

Verilator

Job description

The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems.

Find out more about our culture.

CPU verification engineer driving core level regression debug, triage and responsible for the functional sign-off for the core.

• Functional verification with emphasis on core level regression debug and triage for simulation and emulation regressions
• Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments
• Primary owner for driving bug hunting using all available stimulus generators. Analysis of bugs found and proposing not only stimulus but also configuration and coverage changes
• Drive core level regression environment enhancements to improve the overall productivity for the team
• Develop detailed core level verification plans by understanding both ISA and microarchitectural specifications for the design
• Support design deployment across simulation and emulation platforms
• Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
• Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster
• BS/MS/PhD in EE/ECE/CE/CS with at least 7+ years of experience
• Strong background and experience with high performance OOO CPU microarchitecture
• Experience and understanding of one or more ISAs - x86, ARM or RISCV
• Significant experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug
• Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios
• Familiar with simulation, formal and emulation environments
• Hands-on with scripting (Python, PERL)
• Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
• Strong problem solving and debug skills across various levels of design hierarchies

Locations: Bangalore, India

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.