Staff Engineer, CPU Core Verification

Tenstorrent; Bengaluru; Hybrid; INR 3,000,000 - 5,000,000; Full time

Job summary

Tenstorrent is seeking a seasoned professional for CPU verification in Bengaluru, India. This hybrid role involves ownership of CPU core-level verification, requiring over 8 years in CPU design and verification.

You will plan and execute functional verification for CPU features, develop models in UVM and C/C++, and debug complex scenarios. The position promises a competitive compensation package and an opportunity to work at the forefront of high-performance computing.

Qualifications

• 8+ years in CPU verification or closely related digital design.
• In-depth knowledge of high-performance out-of-order CPU microarchitecture.
• Comfortable with RTL, waveforms, logs, and complex debug scenarios.

Responsibilities

• Plan and drive functional verification for CPU core features and complex microarchitectural scenarios.
• Develop UVM and C/C++ based stimulus and coverage models.
• Debug simulation and emulation regressions using RTL understanding.
• Build and enhance coverage models and debug infrastructure.
• Collaborate with design, validation, and test teams for CPU delivery.

Skills

CPU verification

High-performance CPU microarchitecture

RTL debugging

Communication across teams

Tools

UVM

C/C++

Job description

At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.

This role is hybrid, based out of Bangalore, India.

Who You Are

• You bring 8+ years in CPU verification or closely related digital design.
• You know high‑performance out‑of‑order CPU microarchitecture in depth.
• You work comfortably with RTL, waveforms, logs, and complex debug scenarios.
• You communicate clearly across design, DV, emulation, and post‑silicon teams.

What We Need

• Plan and drive functional verification for CPU core features and complex microarchitectural scenarios.
• Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC‑V extensions, and un‑core components.
• Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently.
• Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure.
• Collaborate with design, validation, and test teams to support bring‑up and delivery of robust CPU cores and clusters.

What You Will Learn

• How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.
• Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.
• Ways to scale coverage, debug, and infrastructure across multiple CPU programs.
• How open hardware and software fit into Tenstorrent’s broader compute roadmap.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.