Associate Staff Physical Design Engineer

Silicon Labs; Hyderabad; On-site; INR 3,500,000 - 7,000,000; Full time

Benefits offered by this job

Equity Rewards (RSUs)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs is seeking a seasoned DFT engineer to contribute to the design-for-test architecture for complex SoCs. You will shape the DFT flow across scan, JTAG, MBIST, and at-speed testing, collaborating with cross-functional teams to ensure robust silicon bring-up and production readiness.

The role requires hands-on experience with RTL design, Python/Perl scripting, and DFT tools. You will optimize test time, expand coverage, and maintain thorough test documentation across global teams.

Qualifications

• 8+ years of DFT/ASIC/SoC design experience.
• Experience with cross-functional and global teams.
• Exposure to ATE platforms is a plus.
• Strong debugging and problem-solving skills.
• Good communication and collaboration skills.

Responsibilities

• Contribute to DFT architecture including scan, JTAG, boundary scan, MBIST, and at-speed testing.
• Implement and integrate DFT features at block and SoC level.
• Support ATPG pattern generation, simulation, and debug.
• Collaborate with design, verification, physical design, and test teams.
• Work on scan coverage improvement and test time optimization.
• Support silicon bring-up, ATE validation, and failure debug.
• Maintain DFT documentation and test collateral.

Skills

DFT concepts

ATPG

JTAG

RTL design

Scripting

Cross-functional collaboration

Education

Electrical/Computer Engineering degree

Tools

Tessent

DFT Compiler

Advantest

Teradyne

Job description

Job Description:

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

The Role:

This position involves contributing to Design-for-Test (DFT) architecture and implementation for complex SoCs, including multi-core processors, memory subsystems, and high-speed interfaces. The candidate will work on scan, ATPG, MBIST, and JTAG-based test solutions, and collaborate with cross-functional teams to support silicon bring-up, validation, and production.

Responsibilities:

• Contribute to DFT architecture including scan, JTAG, boundary scan, MBIST, and at-speed testing


• Implement and integrate DFT features at block and SoC level


• Support ATPG pattern generation, simulation, and debug


• Collaborate with design, verification, physical design, and test teams


• Work on scan coverage improvement and test time optimization


• Support silicon bring-up, ATE validation, and failure debug


• Maintain DFT documentation and test collateral

Requirements:

• Strong understanding of DFT concepts for multi-clock SoC designs


• Experience with ATPG for stuck-at, transition, and other fault models


• Hands-on experience with DFT tools (Tessent, DFT Compiler, or similar)


• Familiarity with JTAG and boundary scan


• Knowledge of low-power DFT and MBIST concepts


• Exposure to RTL design and integration (Verilog/SystemVerilog)


• Scripting skills (Python/Perl/Tcl/shell)

Qualifications:

• Bachelor’s or Master’s degree in Electrical or Computer Engineering


• 8+ years of experience in DFT/ASIC/SoC design


• Experience working with cross-functional and global teams


• Exposure to ATE platforms (Advantest, Teradyne) is a plus


• Strong debugging, analytical, and problem-solving skills


• Good communication and collaboration skills

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Equity Rewards (RSUs)


• Insurance plans with Outpatient cover


• National Pension Scheme (NPS)


• Flexible work policy


• Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Requirements: