ASIC Verification Engineer

Hewlett Packard Enterprise Development LP; India; On-site; INR 1,500,000 - 2,100,000; Full time

Benefits offered by this job

Health & Wellbeing

Personal & Professional Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise is seeking an ASIC Verification Engineer to design and maintain verification environments using SystemVerilog and UVM, working onsite from an HPE office in India, and collaborating with RTL, software, and firmware teams.

The role emphasizes constrained-random verification, code and functional coverage analysis, and tape-out signoff, with tooling like VCS and NC/Xcelium and scripting in Perl, Python, Tcl or Shell.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field (BSEE/MSEE).
• 3+ years of experience in ASIC/SoC verification.
• Strong expertise in SystemVerilog‑based ASIC verification.
• Hands‑on experience with UVM, OVM, or VMM verification methodologies.
• Knowledge of constrained‑random verification techniques.
• Experience with simulation and debugging using tools such as VCS or NC/Xcelium.
• Solid understanding of functional coverage, code coverage, and verification signoff processes.
• Strong ASIC debugging, problem‑solving, and root‑cause analysis skills.
• Scripting experience in Perl, Tcl, Python, and/or Shell scripting.
• Familiarity with Ethernet and networking protocol verification is a plus.

Responsibilities

• Develop and maintain ASIC verification environments using SystemVerilog and UVM methodologies.
• Architect and implement block-level, subsystem-level, and full-chip verification environments.
• Create, execute, and deliver comprehensive verification test suites for ASIC designs.
• Perform functional verification using industry-standard simulators such as VCS and NC/Xcelium.
• Verify complex ASIC blocks independently and drive them to tape-out signoff.
• Analyze and close code coverage, functional coverage, and support gate-level simulations (GLS).
• Debug and resolve design issues by collaborating closely with RTL designers and software/firmware teams.
• Enhance verification productivity by developing Perl, Python, Tcl, or Shell scripts for automation and infrastructure improvements.
• Contribute to the adoption and application of advanced verification methodologies, including constrained-random verification and UVM-based verification flows.

Skills

SystemVerilog

UVM

Constrained-random verification

VCS

NC/Xcelium

Functional coverage

Code coverage

Verification signoff

Perl

Python

Tcl

Shell scripting

Networking protocol verification

Education

Bachelor's or Master's degree in Electrical/Electronics Engineering (BSEE/MSEE)

Tools

VCS

NC/Xcelium

Job description

ASIC Verification Engineer

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description

What You’ll Do

Develop and maintain ASIC verification environments using SystemVerilog and UVM methodologies. Architect and implement block-level, subsystem-level, and full-chip verification environments. Create, execute, and deliver comprehensive verification test suites for ASIC designs. Perform functional verification using industry-standard simulators such as VCS and NC/Xcelium. Verify complex ASIC blocks independently and drive them to tape-out signoff. Analyze and close code coverage, functional coverage, and support gate-level simulations (GLS). Debug and resolve design issues by collaborating closely with RTL designers and software/firmware teams. Enhance verification productivity by developing Perl, Python, Tcl, or Shell scripts for automation and infrastructure improvements. Contribute to the adoption and application of advanced verification methodologies, including constrained-random verification and UVM-based verification flows.

What You Need to Bring

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field (BSEE/MSEE).
• 3+ years of experience in ASIC/SoC verification.
• Strong expertise in SystemVerilog‑based ASIC verification.
• Hands‑on experience with UVM, OVM, or VMM verification methodologies.
• Knowledge of constrained‑random verification techniques.
• Experience with simulation and debugging using tools such as VCS or NC/Xcelium.
• Solid understanding of functional coverage, code coverage, and verification signoff processes.
• Strong ASIC debugging, problem‑solving, and root‑cause analysis skills.
• Scripting experience in Perl, Tcl, Python, and/or Shell scripting.
• Familiarity with Ethernet and networking protocol verification is a plus.
• Ability to work effectively in a cross‑functional environment with design and software teams.

What We Can Offer You

• Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
• Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
• Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Job: Engineering Job Level: TCP_02

Equal Employment Opportunity

HPE is an Equal Employment Opportunity / Veterans / Disabled / LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.

EEO and Hiring Practices

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

Equal Opportunity Employer (EEO)

Hewlett Packard Enterprise provides equal employment opportunity to any employee or applicant without regard to sex, gender, color, race, ethnicity, religion, creed, national origin, ancestry, citizenship, age, marital status, sexual orientation, gender identity and expression, physical or mental disability, medical condition, pregnancy, protected veteran status, uniformed service status, familial status, genetic information, political affiliation, or any other characteristic protected by federal, state, or local law.

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Accessibility

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