ASIC Engineer | Physical Design, CAD Methodology | STA Setup, Convergence Methodology | Exp 4+ years

123 Cisco Systems (India) Private Limited; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Cisco Systems (India) Private Limited in Bengaluru is seeking an experienced ASIC Physical Design Engineer to join the SiliconOne team. You will lead backend implementation from RTL to GDS, focusing on floor planning, place & route, timing closure, and power integrity, with emphasis on performance and die size.

The role requires 4+ years in ASIC physical design, strong debugging, and scripting for STA tool methodologies.

Qualifications

• Bachelor's or Master’s Degree in Electrical or Computer Engineering with 4+ years of experience.
• ASIC physical implementation including floor planning, clock/power distribution, global signal planning, I/O planning and hard IP integration.
• Hierarchical design implementation, timing closure, physical convergence.
• Automation scripting within STA tools for methodology development.
• Excellent debugging skills and Power Integrity analysis.
• STA setup, convergence, and sign-off for Multi-Mode and Multi-Corner designs.
• Experience with large designs (>100M gates) on sub 16/14/7/5/3/2nm nodes.

Responsibilities

• Drive backend process through RTL to GDS flow, including floor planning, place & route, timing closure, and physical verification.
• Focus on performance and die size optimization.
• Collaborate with the physical design team to streamline methodologies and improve flows.

Skills

ASIC Physical Design

Floor planning

Timing closure

Power integrity

STA automation scripting

Debugging

Large-scale designs (>100M gates)

Education

Bachelor's or Master’s Degree in Electrical or Computer Engineering

Tools

Primetime

STA tools

ECO flows

Job description

Meet the Team

Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Your Impact

Our creative and talented Physical Design team in Bangalore, India. As a member of this team, you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.

Minimum Qualifications

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with 4+ Years of exp
• All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
• Hierarchical design implementation approach, Timing closure, physical convergence.
• Work on Automation scripts within STA tools for Methodology development.
• Excellent debugging skills in implementation issues and ability to produce creative solutions, Power Integrity Analysis.
• STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
• Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3/2nm technologies.

Preferred Qualifications

Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Evaluate multiple timing methodologies/tools on different designs and technology nodes.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cisconians power the future. We make impact as a team, innovating fast and fearlessly to create meaningful solutions on a large scale. The depth and breadth of our technology doesn't just benefit our customers – it also means limitless opportunities for us to experiment and learn. We understand the power each of our unique backgrounds bring when we work together. Because of that, we have a global network of thinkers, doers, experts, and curious creators who help one another do their life’s best work.