ASIC Design Verification Engineer

The Consensus; Bengaluru; On-site; INR 3,000,000 - 4,500,000; Full time

Job summary

Cisco is seeking an experienced ASIC Design Verification Engineer for our Bengaluru-based team. You will craft DV environments for blocks, clusters and top-level integration, building infrastructure from scratch and maintaining it across the design lifecycle.

You will collaborate with designers and software teams to debug issues, verify RTL with gate-level simulations, and lead the ASIC bring-up and verification coverage efforts, including emulation testing.

Qualifications

• 7+ years of ASIC design verification experience.
• Proficient in UVM/SystemVerilog with test bench development.
• Experience with block, cluster and top-level verification.
• Hands-on with SystemVerilog constraints, structures and classes.

Responsibilities

• Architect DV environments for blocks, clusters and top level.
• Develop DV infrastructure from scratch and maintain it.
• Collaborate with designers, architects and software teams to debug issues.
• Support testing of design in emulation and bring-up.
• Lead all aspects of ASIC bring-up and verification coverage.

Skills

UVM/SystemVerilog

ASIC verification

Testbench development

Constraint random stimulus

RTL debugging

Education

Bachelor's degree in EE/CE

Tools

Veloce

Palladium

Zebu

HAPS

Job description

## ASIC Design Verification EngineerApplyremote type: Onsite Onlylocations: Bangalore, Indiatime type: Full timeposted on: Posted 30+ Days Agojob requisition id: 2008234**Meet the Team:** The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. **Your Impact:*** You will contribute to developing Cisco’s progressive data center by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:* Architect block, cluster and top-level DV environment infrastructure.* Develop DV infrastructure from scratch.* Maintain and improve existing DV environments.* Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus.* Ensure complete verification coverage through implementation and review of code and functional coverage.* Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.* Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance.* Support testing of design in emulation.* Lead all aspects of and manage the ASIC bring-up process.**Minimum Qualification:*** Bachelor’s Degree or equivalent experience in EE, CE, or other related field.* 7+ years of related ASIC design verification experience.* Proficient in ASIC verification using UVM/System Verilog.* Proficient in verifying sophisticated blocks, clusters and top level for ASIC.* Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.**Preferred Qualifications:*** Scripting experience with Perl and/or Python.* Experience with data path verification, performance tests* Experience with Veloce/Palladium/Zebu/HAPS.* Formal verification (iev/vc formal) knowledge.* Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).# Why Cisco?At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.We are Cisco, and our power starts with you.