Analog/Power IC Design Engineer – IP Block Owner

Axiro Semiconductor; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Axiro Semiconductor in Bengaluru, India seeks passionate analog and power IC design engineers to own IP blocks like charge pumps, LDOs, bandgaps and drivers for gate drivers, DC-DC converters, and power-management platforms.

You will understand specifications, select topologies, design transistor-level circuits, run thorough simulations, and drive layout, DRC/LVS, parasitic extraction, and post-layout verification. Minimum 1–5 years of relevant experience with strong fundamentals is expected.

Qualifications

• End-to-end ownership over assigned IP blocks from specifications to silicon support.
• Strong analog/power IC design understanding and trade-offs.
• Experience with layout, verification, and sign-offs.

Responsibilities

• Understand IP specifications and challenge ambiguities.
• Choose circuit topology meeting performance, power, area, and robustness.
• Design transistor-level analog/power circuits with proper biasing and protection.
• Perform DC/AC/transient/noise/corner/Monte-Carlo simulations and review results.
• Develop compact layouts with proper matching and parasitic considerations.
• Ensure DRC/LVS integrity before extraction.
• Generate and review extracted parasitics models.
• Re-validate performance post-layout across PVT and critical conditions.
• Lead design reviews with leads and architects covering topology, simulations, layout, and reliability.
• Own block sign-off with documented evidence of meeting requirements.
• Support silicon bring-up, characterization, failure analysis and corrective actions.

Skills

Ownership mindset

Team player

Analog circuit design

Feedback & stability fundamentals

Analog layout

MOSFET physics

Simulation & verification

Debugging & problem solving

Power IC fundamentals

Academics

Experience 1-5 years

Education

MS/M.Tech./Ph.D. in Electrical/Electronics Engineering, Microelectronics or VLSI Design

Tools

Cadence Virtuoso/Spectre

Job description

We are looking for passionate analog/power IC design engineers who will take ownership of individual analog IP blocks like charge pumps, LDOs, bandgaps, bias generators, error amplifiers, level shifters, driver amplifiers, sensing circuits, ADCs, DACs used in Gate Drivers, DC-DC Converter and Intelligent Power-management Platforms.

For each of the IP blocks assigned, the designer in supposed to follow-through the process below:

• Understand & Question IP Specification: Clearly understand all the block-level specifications, challenge ambiguities, and identify key performance, reliability, and implementation constraints.
• Choose Circuit Topology: Evaluate and select the most appropriate circuit architecture/topology to meet performance, power, area and robustness requirements within the technology constraints.
• Circuit Design: Design innovative transistor-level analog/power circuits with appropriate biasing, feedback, compensation, protection, and device-sizing strategies.
• Schematic Simulations & Preliminary Review: Perform thorough DC/AC/transient/noise/corner/Monte-Carlo simulations and get the results critically reviewed against specifications.
• Layout Design: Develop compact, robust layouts with appropriate matching, symmetry, shielding, current-density, IR-drop, and parasitic considerations.
• DRC/LVS: Ensure layout integrity through clean DRC/LVS and resolve all physical verification issues before extraction.
• Extract Parasitics: Generate and review extracted netlists/models to accurately capture layout-dependent parasitic effects.
• Post-Layout Simulations: Re-validate performance across PVT, mismatch, Monte-Carlo, and critical operating conditions using extracted parasitics.
• Critical Design Review: Own rigorous design reviews with senior leads and architects, covering circuit topology, simulations, layout, reliability, corner coverage, risks, and specification compliance.
• Block Sign-off: Own complete block sign-off with documented evidence that all functional, performance, reliability, and physical-design requirements are met.
• Silicon Debug & Support: Support silicon bring-up, characterization, failure analysis, root-cause identification, and corrective actions through product qualification.

Qualifications

• Ownership mindset: Willingness to take end-to-end ownership of assigned IP blocks, from understanding specifications and circuit design through verification, layout, sign-off, and silicon support, with minimal hand-holding.
• Team Player: Ability to work effectively with circuit, layout, verification, systems, and product engineers while understanding and managing interactions between IP blocks within the product.
• Analog Circuit Design: Strong understanding of fundamental analog circuit topologies and the ability to make sound trade-offs across performance, power, area, speed, noise, and robustness.
• Feedback & Stability Fundamentals: Good understanding of feedback concepts, loop gain, stability, frequency response, compensation, poles/zeros, and phase/gain margin.
• Analog Layout: Hands-on experience with analog layout, including matching, common-centroid techniques, shielding, guard rings, parasitic management, DRC/LVS, extraction, and post-layout verification.
• MOSFET Physics: Strong understanding of MOSFET operation, higher-order effects, biasing, device sizing, operating regions, and gm/Id - based design and optimization.
• Simulation & Verification: Proficiency in SPICE-based simulations including DC, AC, transient, noise, PVT corners, mismatch, Monte Carlo, and worst-case analysis, with Cadence Virtuoso/Spectre experience strongly required.
• Debugging & Problem Solving: Ability to systematically analyse simulation failures, unexpected circuit behaviour, specification misses, and layout-induced performance degradation to identify root causes and implement corrective actions.
• Power IC Fundamentals (Desirable, not necessary): Familiarity with BCD process technologies, high-voltage devices, power semiconductor device physics, gate drivers, DC-DC converters, LDOs, protection circuits, or other power-management ICs is a strong plus
• Academics: M.S./M.Tech./Ph.D. in Electrical/Electronics Engineering, Microelectronics or VLSI Design.
• Experience: 1-5 years of relevant experience in analog, mixed-signal, or power IC design