Analog/Power IC Design Engineer – IP Block Owner

Axiro; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

Axiro Semiconductor, a Bengaluru-based fabless design company, seeks analog/power IC engineers to own IP blocks such as charge pumps, LDOs, bandgaps, and intelligent power-management platforms. You will drive topology selection, transistor-level design, and post-layout verification across PVT conditions.

You will collaborate with circuit, layout, verification and product teams to ensure sign-off readiness and silicon support, leveraging Cadence tools and SPICE simulations to meet stringent

Qualifications

• Ownership mindset to drive IP blocks end-to-end with minimal guidance.
• Strong team collaboration across circuit, layout, verification, and product teams.
• Deep understanding of analog circuit topologies and trade-offs.
• Knowledge of feedback, stability, and compensation for robust designs.
• Hands-on analog layout experience with matching, shielding and parasitics.
• Solid MOSFET physics, biasing, sizing and gm/Id optimization.
• Proficient SPICE-based simulations including DC/AC/transient/noise.
• Ability to debug and solve complex circuit and simulation issues.
• Familiarity with power IC concepts, HV devices and gate drivers is a plus.

Responsibilities

• Understand IP specifications, challenge ambiguities, identify constraints.
• Select circuit topology to meet performance, power and area goals.
• Design transistor-level analog/power circuits with proper sizing and biasing.
• Perform DC/AC/transient/noise and corner simulations; reviewer alignment.
• Create compact, robust layouts with matching and parasitic considerations.
• Ensure clean DRC/LVS and capture parasitics for extraction.
• Run post-layout simulations across PVT, mismatch and Monte Carlo.
• Lead design reviews with senior leads covering topology, simulations, layout.
• Own block sign-off with evidence of meeting requirements.
• Support silicon bring-up, characterization and failure analysis.

Skills

Ownership mindset

Team Player

Analog circuit design

Feedback & stability

Analog layout

MOSFET physics

Simulation & verification

Debugging & problem solving

Power IC fundamentals

Education

MS/M.Tech/PhD in Electrical/Electronics

Microelectronics or VLSI Design

Tools

Cadence

SPICE

Job description

Axiro Semiconductor is a fabless semiconductor design company headquartered in Bengaluru, driving innovation in RF, wireless infrastructure, satellite communication (Satcom), and high-speed connectivity solutions. Backed by CG Power & Industrial Solutions Ltd. part of the 120-year-old Murugappa Group. Axiro represents India’s leap into the global semiconductor arena. With millions of chips already powering global networks, a world-class team across India, the US, and Europe, and cutting-edge expertise spanning RF, mmWave, GaN, and next-generation communication technologies, Axiro is engineering the future of how the world connects, calculates, and communicates.For more details – www.axiro.com

Job Description

We are looking for passionate analog/power IC design engineers who will take ownership of individual analog IP blocks like charge pumps, LDOs, bandgaps, bias generators, error amplifiers, level shifters, driver amplifiers, sensing circuits, ADCs, DACs used inGate Drivers, DC-DC ConverterandIntelligent Power-managementPlatforms.

Responsibilities

• Understand & Question IP Specification: Clearly understand all the block-level specifications, challenge ambiguities, and identify key performance, reliability, and implementation constraints.
• Choose Circuit Topology: Evaluate and select the most appropriate circuit architecture/topology to meet performance, power, area and robustness requirements within the technology constraints.
• Circuit Design: Design innovative transistor-level analog/power circuits with appropriate biasing, feedback, compensation, protection, and device-sizing strategies.
• Schematic Simulations & Preliminary Review: Perform thorough DC/AC/transient/noise/corner/Monte-Carlo simulations and get the results critically reviewed against specifications.
• Layout Design: Develop compact, robust layouts with appropriate matching, symmetry, shielding, current-density, IR-drop, and parasitic considerations.
• DRC/LVS: Ensure layout integrity through clean DRC/LVS and resolve all physical verification issues before extraction.
• Extract Parasitics: Generate and review extracted netlists/models to accurately capture layout-dependent parasitic effects.
• Post-Layout Simulations: Re-validate performance across PVT, mismatch, Monte-Carlo, and critical operating conditions using extracted parasitics.
• Critical Design Review: Own rigorous design reviews with senior leads and architects, covering circuit topology, simulations, layout, reliability, corner coverage, risks, and specification compliance.
• Block Sign-off: Own complete block sign-off with documented evidence that all functional, performance, reliability, and physical-design requirements are met.
• Silicon Debug & Support: Support silicon bring-up, characterization, failure analysis, root-cause identification, and corrective actions through product qualification.

Requirements

• Ownership mindset: Willingness to take end-to-end ownership of assigned IP blocks, from understanding specifications and circuit design through verification, layout, sign-off, and silicon support, with minimal hand-holding.
• Team Player: Ability to work effectively with circuit, layout, verification, systems, and product engineers while understanding and managing interactions between IP blocks within the product.
• Analog Circuit Design: Strong understanding of fundamental analog circuit topologies and the ability to make sound trade-offs across performance, power, area, speed, noise, and robustness.
• Feedback & Stability Fundamentals: Good understanding of feedback concepts, loop gain, stability, frequency response, compensation, poles/zeros, and phase/gain margin.
• Analog Layout: Hands-on experience with analog layout, including matching, common-centroid techniques, shielding, guard rings, parasitic management, DRC/LVS, extraction, and post-layout verification.
• MOSFET Physics: Strong understanding of MOSFET operation, higher-order effects, biasing, device sizing, operating regions, and gm/Id - based design and optimization.
• Simulation & Verification: Proficiency in SPICE-based simulations including DC, AC, transient, noise, PVT corners, mismatch, Monte Carlo, and worst-case analysis, with Cadence Virtuoso/Spectre experience strongly required.
• Debugging & Problem Solving: Ability to systematically analyse simulation failures, unexpected circuit behaviour, specification misses, layout-induced performance degradation to identify root causes and implement corrective actions.
• Power IC Fundamentals (Desirable, not necessary): Familiarity with BCD process technologies, high-voltage devices, power semiconductor device physics, gate drivers, DC-DC converters, LDOs, protection circuits, or other power-management ICs is a strong plus
• Academics: M.S./M.Tech./Ph.D. in Electrical/Electronics Engineering, Microelectronics or VLSI Design.
• Experience: 1–5 years of relevant experience in analog, mixed-signal, or power IC design

Job Title