Analog Design Engineer

HrdWyr; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

HrdWyr in Bengaluru seeks an experienced Analog IP Design engineer to drive specifications, architecture, and verification across multiple IP blocks. The role focuses on high-performance data converters, power management, and clocking IPs with emphasis on low-noise, low-power implementations.

The candidate should have 10+ years of hands-on experience in Analog IP design, familiarity with SAR/Delta-Sigma converters, PLLs, oscillators, GPIOs, and AMS simulations in SoC contexts.

Qualifications

• 10+ years of experience in Analog IP Design.
• Experience with High Performance Data Converters (SAR, Delta-Sigma), DC-DC converters, PLLs and oscillators.
• Strong knowledge of low power, low noise techniques, ESD, package and board interfaces.
• Experience with Matlab, Verilog modelling and AMS simulations at SoC.

Responsibilities

• Drive specifications, architecture and design of Analog IPs.
• Design and validate multiple Analog IPs including Data Converters, Power Management (Battery Charging), Clocking IPs, and other Analog IPs.
• Collaborate with teams to ensure low-noise, power-efficient implementations.

Skills

Analog IP Design

Data Converters

DC-DC Converters

PLL/Oscillators

GPIOs

AMS Simulation

Verilog Modelling

MATLAB

Tools

AMS Simulators

Job description

• Drive Specifications, Architecture and Design of Analog IPs.
• Design and Validate multiple Analog IPs like Data Converters, Power Management including Battery Charging Circuits, Clocking IPs, and other Analog IP's.

Experience Required

• 10 + years of experience in Analog IP Design.
• Experience in High Performance Data Convertors ( SAR , Delta-Sigma ), DC-DC converters, PLLs, Oscillators, GPIOs and other generic IP's. Expertise in more then one domain would be a plus.
• In-depth understanding of low power, low noise circuits design techniques, ESD, Package and Board interface Simulations.
• Expertise in different simulation tools.
• Experience in Matlab , Verilog modelling and AMS Simulations at SoC.