Microcontroller Subsystem Verification Engineer — UVM / ASIC

European Tech Recruit; Cork; On-site; EUR 70,000 - 110,000; Full time

Job summary

European Tech Recruit is seeking a Microcontroller Subsystem Verification Engineer to deploy industry-leading verification methodologies for embedded IP across IoT, Mobile, Auto, XR, and Compute platforms. The role is permanently onsite in Cork, Ireland, and involves developing testbenches and reusable verification environments.

You will work with design, SoC, and validation teams, applying UVM, SystemVerilog, and scripting to ensure thorough coverage and smooth subsystem integration.

Qualifications

• Experience with UVM-based verification of microcontroller IP.
• Proficiency in SystemVerilog and scripting (Perl/Python).
• Knowledge of AMBA protocols and constrained-random verification.

Responsibilities

• Deploy UVM and formal verification methodologies across microcontroller subsystem IP.
• Develop testbenches and verification components including UVCs, C models, and reusable environments.
• Ensure comprehensive coverage and address gaps with design teams.

Skills

UVM

SystemVerilog

Perl scripting

Python scripting

ARM/ RISC-V verification

Constrained-random

AMBA protocols

Formal verification

Testbench development

SoC collaboration

Tools

UVM tooling

Jasper Formal

VC Formal

Job description

Microcontroller Subsystem Verification Engineer — UVM / ASIC

We are partnered with a global leader in semiconductor and wireless technology innovation. The team is looking to hire a Microcontroller Subsystem Verification Engineer to deploy industry-leading verification methodologies for embedded processing IP across IoT, Mobile, Auto, XR, and Compute platforms.

This is a permanent, fully onsite opportunity based in Cork, Ireland.

Key responsibilities for this Microcontroller Subsystem Verification Engineer position:

• Deploy UVM and formal verification methodologies across microcontroller subsystem IP.
• Develop testbenches and verification components including UVCs, C models, and reusable verification environments.
• Ensure comprehensive coverage and collaborate with design teams to address coverage gaps.
• Support subsystem integration including test planning, test vector delivery, and debug.
• Collaborate closely with design, SoC, and validation teams across multiple levels.

Key requirements:

• Familiarity with ARM or RISC-V ISA verification.
• Proficiency in UVM, SystemVerilog, and Perl/Python scripting.
• Knowledge of AMBA bus protocols, power-aware verification, and constrained-random methodologies.
• Experience with formal verification tools (Jasper, VC Formal) a plus.
• Understanding of microcontroller/processor subsystems advantageous.

Keywords: Microcontroller Subsystem Verification Engineer / UVM / Functional Verification / SystemVerilog / ASIC / ARM / RISC-V / AMBA / Formal Verification / Jasper / Constrained Random / Coverage / Python / Perl / SoC / Cork / Ireland / Onsite / Permanent

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