Low-Latency FPGA/ASIC Engineer for Trading Infrastructure

Virtu Financial; Dublin; On-site; EUR 80,000 - 120,000; Full time

Benefits offered by this job

26 days leave

Family support

Health & wellbeing

Life assurance

Gym subsidy

Travel insurance

Catered lunches

Onsite gym

Job summary

Virtu Financial is building a high-performance hardware team to support its low-latency trading platform. The FPGA/ASIC Engineer will design RTL for new trading applications and own end-to-end delivery from spec to production.

You will help improve the verification pipeline while coordinating hardware deployments in live environments. The ideal candidate has a strong RTL background, 2+ years FPGA/ASIC experience, and familiarity with high-speed interfaces and vendor toolchains.

Qualifications

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 2+ years FPGA/ASIC experience; advanced degree may substitute.
• Strong RTL design and verification skills (SystemVerilog/VHDL, cocotb).

Responsibilities

• Design and develop RTL for new low-latency trading applications.
• Own designs end to end, from spec through verification to production deployment.
• Improve the team's build, simulation, and verification infrastructure.
• Coordinate and execute hardware deployments in live production environments.

Skills

RTL design

SystemVerilog/VHDL

Cocotb

FPGA/IC design flows

Xilinx/AMD toolchains

Synopsys

Cadence

High-speed interfaces (PCIe/ETH/AXI)

Python

C++

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Xilinx/AMD tools

Synopsys

Cadence

Vivado/ISE

Job description

Virtu Financial is building a high-performance hardware team to support its low-latency trading platform. The FPGA/ASIC Engineer will design RTL for new trading applications and own end-to-end delivery from spec to production.

You will help improve the verification pipeline while coordinating hardware deployments in live environments. The ideal candidate has a strong RTL background, 2+ years FPGA/ASIC experience, and familiarity with high-speed interfaces and vendor toolchains.