ASIC Design Engineer (RTL) - Visas Supported

European Tech Recruit; Cork; On-site; EUR 90,000 - 120,000; Full time

Job summary

European Tech Recruit partners with a Global Leading Semiconductor company in Cork, Ireland to hire a Digital Design Engineer. You will join the GPU team to shape cutting-edge ASIC blocks and drive architecture exploration.

The role covers RTL design, micro-architecture, verification, and optimization across shader, memory, and interconnect, with emphasis on power, performance, and silicon cost. Collaboration and communication are essential.

Qualifications

• 3–20 years of ASIC/ RTL design experience.
• Experience with Verilog/SystemVerilog design and Synopsys synthesis.
• Low power design experience and test plan development.
• Proficiency in C/C++/Python programming.
• Experience in GPU/ASIC RTL design (GPU/CPU/DSP/ML/video/camera).
• Exposure to graphics APIs (OpenGL, Vulkan, Direct3D).
• Strong communication and teamwork skills.

Responsibilities

• RTL design for GPU architecture blocks across shader, graphics, memory, interconnect.
• Optimize hardware for performance, power, and cost.
• Evaluate hardware feasibility of complex algorithms.
• Develop micro-architecture and specifications for new designs.
• Develop RTL for the new generation design.
• Provide verification and debugging across project cycles.
• Troubleshoot silicon issues related to the design.

Skills

Verilog / SystemVerilog

Synopsys Synthesis

Low Power Design

Test Plan & Coverage

C/C++/Python

GPU/ASIC Architecture

Graphics API (OpenGL / Vulkan / Direct

Communication / Team Player

Education

Job description

Digital Design Engineer

A great opportunity for an experienced ASIC Design Engineer to join a Global Leading Semiconductor company, working alongside their GPU Team in Cork, Ireland.

The Role

• Micro-architect and design RTL for blocks and modules of our GPU architecture across shader processing, graphics pipelines, memory subsystem and interconnect, and power and system level design
• Identify advanced ways to optimize hardware design for better performance, power, and cost
• Evaluate the hardware feasibilities of complex algorithms and requirements
• Develop micro architecture and specification of the new generation design
• Develop RTL for the corresponding micro architecture
• Provide essential verification and debugging activities for the corresponding design throughout the entire project cycles
• Optimize the silicon cost and improve clock speed
• Troubleshoot silicon issues with products relevant to the corresponding design

Requirements

• The team looks for wide range of level and experience, typically from 3 years to 20 years.
• Experience with Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, coverage-based design verification
• Experience with Computer Architecture, Computer Arithmetic, Low power design, C/C++/Python programming languages is desired.
• Experience in designing RTL for GPU, CPU, DSP, Machine-Learning, cache, controller, video, display, camera blocks in ASIC is desired.
• Exposure to Graphics API (OpenGL, Vulkan, Direct3D, etc) is big plus
• Good communication skill and desire to work as a team player

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