Analog / Mixed-Signal SerDes Design Engineer - Cork, Ireland

Qualcomm; Cork; On-site; EUR 65,000 - 85,000; Full time

Job summary

A leading semiconductor company is seeking Analog/Mixed-Signal design engineers to join their team in Cork, Ireland. This role focuses on designing integrated circuits for high-speed applications including SerDes and PLLs. Candidates should have a Master’s or Ph.D. in a relevant field and at least 3 years of experience in analog mixed-signal design. Key responsibilities include circuit design, performance evaluation, and ensuring best layout practices. The position offers a chance to work with cutting-edge technology in a collaborative environment.

Qualifications

• At least 2 years of ASIC design or verification experience.
• Strong understanding of device physics and IC design tools.
• Experience in high-speed wireline design preferred.

Responsibilities

• Architecture and design of analog/mixed-signal hard macros for SerDes.
• Perform custom circuit designs in FinFET CMOS technologies.
• Create behavioral models in Verilog and run circuit simulations.

Skills

Transistor-level analog mixed-signal design

Experience in SPICE simulators

Designing op-amps and VCO

High-speed SerDes block-level designs

Scripting for automation

Education

Master’s or Ph.D. degree in Science or Engineering

Bachelor's degree in Science or Engineering

Job description

Company:

QT Technologies Ireland Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

About the role

Qualcomm’s SerDes PHY team is seeking Analog / Mixed‑Signal design engineers to join our growing team in Cork, Ireland. The successful candidate will work on analog and mixed‑signal integrated circuits for high‑speed PHY receivers and drivers, VCOs, PLLs and a range of other custom IP for Qualcomm Mobile, Auto, IoT & Compute SoC products. The primary focus is on low‑power and low‑voltage mixed‑signal design with emphasis on advanced nanometer FinFET and GAA technology nodes.

The successful candidate will both design key circuit blocks and work closely with layout engineers to ensure the layout is fully optimised and complies with best analog layout practices. You will be directly involved in delivering next‑generation SerDes and PLL designs for Qualcomm SoCs and part of a large analog mixed‑signal design team involved in architecture analysis and IP delivery in leading‑edge FinFET and GAA process technology nodes at 3 nm and below.

The role requires industry experience in transistor‑level circuit implementations or highly relevant academic experience in a Masters’ or PhD programme focused on full custom analog circuit design using nanometer CMOS technologies. In addition to Analog and Mixed‑Signal circuit design expertise, good understanding of device physics, analog circuit custom layout, power distribution networks (PDN), mixed‑signal design flow, SoC top‑level integration and IC design tools are desired.

Responsibilities:

• Architecture, design, and development of analog / mixed‑signal hard macros for the SerDes IP design team
• Perform custom circuit design in the latest FinFET CMOS process technologies and beyond to support the delivery of SerDes IP
• Participate in internal customer requirements discussions
• Create design specifications
• Create behavioural models in Verilog
• Set‑up, run and analyse circuit simulations
• Perform quality assurance procedures on developed hard macros
• Deliver hard macros and support customer integration and testing
• Perform silicon characterization analysis and prepare silicon verification reports

Skills and Experience we would love to see:

• Master’s or Ph.D. degree in Science, Engineering, or related field
• A minimum of 3‑years of transistor‑level analog mixed‑signal design experience, preferably in high‑speed wireline SerDes, PLL, DDR or other high‑speed applications
• Experience in SPICE simulators and schematic capture tools
• Experience in designing op‑amps, bandgaps, differential amplifiers, VCO, PLL, DLL
• Experience in high‑speed SerDes block‑level designs such as transmitters, receivers, high‑speed VGA, CTLE, CDR, etc.
• Understanding of signal integrity in high‑speed wireline design is preferred
• Scripting to automate circuit design and verification work
• Full‑custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign‑off
• Excellent communication skills and ability to contribute strongly within a high‑performance team

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field
• 2+ years ASIC design, verification, or related work experience

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfil the principal duties of the role and possesses the required competencies.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

If you would like more information about this role, please contact Qualcomm Careers.