Analog Design Engineer - SERDES

Apple Inc.; Dublin; On-site; EUR 90,000 - 140,000; Full time

Job summary

Apple Inc. in Dublin seeks an IC Designer to develop high-performance AMS circuits for SerDes PHY.

You will evaluate topologies, translate specifications into transistor‑level implementations, and drive layout supervision while collaborating with architecture, packaging, and SOC teams. The role emphasizes analog mixed‑signal design, including bandgap references, LDOs, amplifiers, DAC/ADCs, and high‑speed interfaces, with a focus on timing closure, testing, and robust characterization to deliver

Qualifications

• Deep knowledge of analog mixed-signal design and high-speed links.
• Experience with Bandgap, LDOs, amplifiers, DACs/ADCs, oscillators.
• Familiarity with timing closure and lab testing.
• Proficiency in SystemVerilog, Matlab, Python for modelling.

Responsibilities

• Develop AMS circuits for SerDes PHY with emphasis on PPA.
• Evaluate circuit topologies and carry designs from specs to layout.
• Drive layout supervision and work with SOC, packaging, and architecture teams.
• Perform bench evaluation and characterization to validate IP quality.

Skills

AMS design

High-speed SerDes

Analog mixed‑signal

Circuit modelling

Layout supervision

Education

PhD/Master in Electrical Engineering

Job description

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At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking IC Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day.

Description

In this role, you will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO) with best in class power, performance, and area (PPA).You will work with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create block-level specifications and execute on transistor-level implementation and behavioral modelling. You will drive mask design to implement layout view of designs. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these sophisticated IPs, on regular basis you will interact with your peers/management to communicate progress and discuss new ideas making it a lively and interactive work environment.

Minimum Qualifications

• The ideal candidate should have deep understanding of analog mixed-signal design with experience in high-speed serial links.
• Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
• Solid understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
• Good grasp and understanding of digitally assisted analog design concepts (e.g. background calibrations, LMS-based adaptive loops)
• Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts
• Knowledge of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 20+ Gbps NRZ and PAM applications
• Knowledge of CDR architectures and implementations
• Knowledge of lab equipments and testing
• Experience in Analog Mixed Signal circuit modelling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
• Hands-on experience in advanced CMOS technologies, design with FinFet technology
• Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
• Experience in the following areas is a plus
• Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
• Experience in lab testing of high-speed serial I/O, debug and data analysis techniques
• Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY)
• Skills in scripting and automation to enhance efficiency are highly desirable

Preferred Qualifications

• PhD/master's degree in Electric Engineering or relevant experience
• Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

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